Datasheet Texas Instruments CDC2536DBRG4 — 数据表
| 制造商 | Texas Instruments |
| 系列 | CDC2536 |
| 零件号 | CDC2536DBRG4 |
具有1 / 2x，1x和2x频率选项的3.3V PLL时钟驱动器28-SSOP
数据表
CDC2536: 3.3-V PLL Clock Driver With 3-State Outputs datasheet
PDF, 446 Kb, 修订版: E, 档案已发布: Jul 9, 2004
从文件中提取
价格
状态
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
打包
| Pin | 28 |
| Package Type | DB |
| Industry STD Term | SSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Device Marking | CDC2536 |
| Width (mm) | 5.3 |
| Length (mm) | 10.2 |
| Thickness (mm) | 1.95 |
| Pitch (mm) | .65 |
| Max Height (mm) | 2 |
| Mechanical Data | 下载 |
参数化
| Absolute Jitter (Peak-to-Peak Cycle or Period Jitter) | 200 ps |
| Number of Outputs | 6 |
| Operating Frequency Range(Max) | 100 MHz |
| Operating Frequency Range(Min) | 25 MHz |
| Package Group | SSOP |
| Package Size: mm2:W x L | 28SSOP: 80 mm2: 7.8 x 10.2(SSOP) PKG |
| Rating | Catalog |
| VCC | 3.3 V |
| t(phase error) | 500 ps |
| tsk(o) | 500 ps |
生态计划
| RoHS | Compliant |
应用须知
- Application and Design Considerations for CDC5xx Phase-Lock Loop Clock DriversPDF, 101 Kb, 档案已发布: Apr 1, 1996
Today?s high-speed system designs require stringent propagation and skew parameters to maintain desired system performance. TI developed the CDC5XX platform of PLL clock drivers to meet the need for high-performance clock system components. This document describes the features and functions of the CDC5XX and discusses design considerations and configurations for the CDC586, CDC582, and CDC2582 clo
模型线
系列: CDC2536 (4)
- CDC2536DB CDC2536DBG4 CDC2536DBR CDC2536DBRG4
制造商分类
- Semiconductors > Clock and Timing > Clock Buffers > Zero Delay Buffers