Datasheet Texas Instruments CDC2536 — 数据表
制造商 | Texas Instruments |
系列 | CDC2536 |
具有1 / 2x,1x和2x频率选项的3.3V PLL时钟驱动器
数据表
CDC2536: 3.3-V PLL Clock Driver With 3-State Outputs datasheet
PDF, 446 Kb, 修订版: E, 档案已发布: Jul 9, 2004
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价格
状态
CDC2536DB | CDC2536DBG4 | CDC2536DBR | CDC2536DBRG4 | |
---|---|---|---|---|
Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
Manufacture's Sample Availability | Yes | No | Yes | No |
打包
CDC2536DB | CDC2536DBG4 | CDC2536DBR | CDC2536DBRG4 | |
---|---|---|---|---|
N | 1 | 2 | 3 | 4 |
Pin | 28 | 28 | 28 | 28 |
Package Type | DB | DB | DB | DB |
Industry STD Term | SSOP | SSOP | SSOP | SSOP |
JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G |
Package QTY | 50 | 50 | 2000 | 2000 |
Carrier | TUBE | TUBE | LARGE T&R | LARGE T&R |
Device Marking | CDC2536 | CDC2536 | CDC2536 | CDC2536 |
Width (mm) | 5.3 | 5.3 | 5.3 | 5.3 |
Length (mm) | 10.2 | 10.2 | 10.2 | 10.2 |
Thickness (mm) | 1.95 | 1.95 | 1.95 | 1.95 |
Pitch (mm) | .65 | .65 | .65 | .65 |
Max Height (mm) | 2 | 2 | 2 | 2 |
Mechanical Data | 下载 | 下载 | 下载 | 下载 |
参数化
Parameters / Models | CDC2536DB | CDC2536DBG4 | CDC2536DBR | CDC2536DBRG4 |
---|---|---|---|---|
Absolute Jitter (Peak-to-Peak Cycle or Period Jitter), ps | 200 | 200 | 200 | 200 |
Number of Outputs | 6 | 6 | 6 | 6 |
Operating Frequency Range(Max), MHz | 100 | 100 | 100 | 100 |
Operating Frequency Range(Min), MHz | 25 | 25 | 25 | 25 |
Package Group | SSOP | SSOP | SSOP | SSOP |
Package Size: mm2:W x L, PKG | 28SSOP: 80 mm2: 7.8 x 10.2(SSOP) | 28SSOP: 80 mm2: 7.8 x 10.2(SSOP) | 28SSOP: 80 mm2: 7.8 x 10.2(SSOP) | 28SSOP: 80 mm2: 7.8 x 10.2(SSOP) |
Rating | Catalog | Catalog | Catalog | Catalog |
VCC, V | 3.3 | 3.3 | 3.3 | 3.3 |
t(phase error), ps | 500 | 500 | 500 | 500 |
tsk(o), ps | 500 | 500 | 500 | 500 |
生态计划
CDC2536DB | CDC2536DBG4 | CDC2536DBR | CDC2536DBRG4 | |
---|---|---|---|---|
RoHS | Compliant | Compliant | Compliant | Compliant |
应用须知
- Application and Design Considerations for CDC5xx Phase-Lock Loop Clock DriversPDF, 101 Kb, 档案已发布: Apr 1, 1996
Today?s high-speed system designs require stringent propagation and skew parameters to maintain desired system performance. TI developed the CDC5XX platform of PLL clock drivers to meet the need for high-performance clock system components. This document describes the features and functions of the CDC5XX and discusses design considerations and configurations for the CDC586, CDC582, and CDC2582 clo
模型线
系列: CDC2536 (4)
制造商分类
- Semiconductors> Clock and Timing> Clock Buffers> Zero Delay Buffers