Datasheet Texas Instruments CDC2586PAH — 数据表

具有1 / 2x，1x和2x频率选项的3.3V PLL CLock驱动器52-TQFP

数据表

PDF, 307 Kb, 修订版: D, 档案已发布: Apr 19, 2004

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Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	Yes

Absolute Jitter (Peak-to-Peak Cycle or Period Jitter)	200 ps
Number of Outputs	12
Operating Frequency Range(Max)	100 MHz
Operating Frequency Range(Min)	25 MHz
Package Group	TQFP
Package Size: mm2:W x L	52TQFP: 144 mm2: 12 x 12(TQFP) PKG
Rating	Catalog
VCC	3.3 V
t(phase error)	500 ps
tsk(o)	500 ps

RoHS

Compliant

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PDF, 51 Kb, 修订版: A, 档案已发布: Mar 1, 1997
This document provides an overview of a PLL clock driver. The advantages and disadvantages of PLLs and the cost in designs are discussed. TI manufactures three low-voltage high-performance PLL clock drivers, the CDC2582, CDC2586, and the CDC2586.
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Application and Design Considerations for CDC5xx Phase-Lock Loop Clock Drivers
PDF, 101 Kb, 档案已发布: Apr 1, 1996
Today?s high-speed system designs require stringent propagation and skew parameters to maintain desired system performance. TI developed the CDC5XX platform of PLL clock drivers to meet the need for high-performance clock system components. This document describes the features and functions of the CDC5XX and discusses design considerations and configurations for the CDC586, CDC582, and CDC2582 clo

系列: CDC2586 (2)