CDC319
1-LINE TO 10-LINE CLOCK DRIVER
WITH I2C CONTROL INTERFACE
SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001 D
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D High-Speed, Low-Skew 1-to-10 Clock Buffer
for SDRAM (Synchronous DRAM) Clock
Buffering Applications
Output Skew, tsk(o), Less Than 250 ps
Pulse Skew, tsk(p), Less Than 500 ps
Supports up to Two Unbuffered SDRAM
DIMMs (Dual Inline Memory Modules)
I2C Serial Interface Provides Individual
Enable Control for Each Output
Operates at 3.3 V
Distributed VCC and Ground Pins Reduce
Switching Noise …
