Datasheet Texas Instruments CDC5806PW — 数据表

CDC5806
www.ti.com SCAS760A – MARCH 2004 – REVISED JULY 2004 THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS
FEATURES High Performance Clock Generator
Clock Input Compatible With LVCMOS/LVTTL
Requires a 54-MHz Input Clock to Generate
Multiple Output Frequencies
Low Jitter for Clock Distribution
Generates the Following Clocks:
– VIDCLK 74.175824 MHz/54 MHz
(Buffered)
– AUDCLK 16.9344 MHz/12.288 MHz
– CPUCLK 64 MHz
– ASICCLK 32 MHz
– USBCLK 48 MHz
– MCCLK 38.4 MHz/19.2 MHz/12 MHz
Operates From Single 3.3-V Supply
Low Peak-to-Peak Period Jitter (150 ps
Max)
PLLs Are Powered Down, if No Valid REF_IN
Clock (< 5 MHz) is Detected or the
VDD is Below 2 V
PLL Loop Filter Components Integrated
Packaged in TSSOP (PW) 20-Pin Package …