Datasheet Texas Instruments CDC582 — 数据表
制造商 | Texas Instruments |
系列 | CDC582 |
具有LVPECL输出和LVTTL输出且具有1 / 2x,1x和2x频率选项的3.3V PLL时钟驱动器
数据表
3.3-V Phase-Lock Loop Clock Driver With Differential LVPECL Clock Inputs datasheet
PDF, 150 Kb, 修订版: B, 档案已发布: Feb 1, 1996
从文件中提取
价格
状态
CDC582PAH | CDC582PAHG4 | |
---|---|---|
Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) |
Manufacture's Sample Availability | Yes | Yes |
打包
CDC582PAH | CDC582PAHG4 | |
---|---|---|
N | 1 | 2 |
Pin | 52 | 52 |
Package Type | PAH | PAH |
Industry STD Term | TQFP | TQFP |
JEDEC Code | S-PQFP-G | S-PQFP-G |
Package QTY | 160 | 160 |
Carrier | JEDEC TRAY (10+1) | JEDEC TRAY (10+1) |
Device Marking | CDC582 | CDC582 |
Width (mm) | 10 | 10 |
Length (mm) | 10 | 10 |
Thickness (mm) | 1 | 1 |
Pitch (mm) | .65 | .65 |
Max Height (mm) | 1.2 | 1.2 |
Mechanical Data | 下载 | 下载 |
参数化
Parameters / Models | CDC582PAH | CDC582PAHG4 |
---|---|---|
Absolute Jitter (Peak-to-Peak Cycle or Period Jitter), ps | 200 | 200 |
Number of Outputs | 12 | 12 |
Operating Frequency Range(Max), MHz | 100 | 100 |
Operating Frequency Range(Min), MHz | 25 | 25 |
Package Group | TQFP | TQFP |
Package Size: mm2:W x L, PKG | 52TQFP: 144 mm2: 12 x 12(TQFP) | 52TQFP: 144 mm2: 12 x 12(TQFP) |
Rating | Catalog | Catalog |
VCC, V | 3.3 | 3.3 |
t(phase error), ps | 500 | 500 |
tsk(o), ps | 500 | 500 |
生态计划
CDC582PAH | CDC582PAHG4 | |
---|---|---|
RoHS | Compliant | Compliant |
应用须知
- Application and Design Considerations for CDC5xx Phase-Lock Loop Clock DriversPDF, 101 Kb, 档案已发布: Apr 1, 1996
Today?s high-speed system designs require stringent propagation and skew parameters to maintain desired system performance. TI developed the CDC5XX platform of PLL clock drivers to meet the need for high-performance clock system components. This document describes the features and functions of the CDC5XX and discusses design considerations and configurations for the CDC586, CDC582, and CDC2582 clo
模型线
系列: CDC582 (2)
制造商分类
- Semiconductors> Clock and Timing> Clock Buffers> Zero Delay Buffers