Datasheet Texas Instruments CDC586PAHG4 — 数据表
| 制造商 | Texas Instruments |
| 系列 | CDC586 |
| 零件号 | CDC586PAHG4 |
具有1 / 2x，1x和2x频率选项的3.3V PLL时钟驱动器52-TQFP
数据表
CDC586: 3.3-V PLL Clock Driver With 3-State Outputs datasheet
PDF, 305 Kb, 修订版: E, 档案已发布: Apr 19, 2004
从文件中提取
价格
状态
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
打包
| Pin | 52 |
| Package Type | PAH |
| Industry STD Term | TQFP |
| JEDEC Code | S-PQFP-G |
| Package QTY | 160 |
| Carrier | JEDEC TRAY (10+1) |
| Device Marking | CDC586 |
| Width (mm) | 10 |
| Length (mm) | 10 |
| Thickness (mm) | 1 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | 下载 |
参数化
| Absolute Jitter (Peak-to-Peak Cycle or Period Jitter) | 200 ps |
| Number of Outputs | 12 |
| Operating Frequency Range(Max) | 100 MHz |
| Operating Frequency Range(Min) | 25 MHz |
| Package Group | TQFP |
| Package Size: mm2:W x L | 52TQFP: 144 mm2: 12 x 12(TQFP) PKG |
| Rating | Catalog |
| VCC | 3.3 V |
| t(phase error) | 500 ps |
| tsk(o) | 500 ps |
生态计划
| RoHS | Compliant |
应用须知
- Phase-Lock Loop-Based (PLL) Clock Drivers: Benefits Versus Costs (Rev. A)PDF, 51 Kb, 修订版: A, 档案已发布: Mar 1, 1997
This document provides an overview of a PLL clock driver. The advantages and disadvantages of PLLs and the cost in designs are discussed. TI manufactures three low-voltage high-performance PLL clock drivers, the CDC2582, CDC2586, and the CDC2586. - Application and Design Considerations for CDC5xx Phase-Lock Loop Clock DriversPDF, 101 Kb, 档案已发布: Apr 1, 1996
Today?s high-speed system designs require stringent propagation and skew parameters to maintain desired system performance. TI developed the CDC5XX platform of PLL clock drivers to meet the need for high-performance clock system components. This document describes the features and functions of the CDC5XX and discusses design considerations and configurations for the CDC586, CDC582, and CDC2582 clo
模型线
制造商分类
- Semiconductors > Clock and Timing > Clock Buffers > Zero Delay Buffers