Datasheet Texas Instruments CDC706PWG4 — 数据表

定制编程的3-PLL时钟合成器/乘法器/分频器20-TSSOP

数据表

PDF, 1.4 Mb, 修订版: B, 档案已发布: Feb 11, 2008

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Lifecycle Status	NRND (Not recommended for new designs)
Manufacture's Sample Availability	No

RoHS

Compliant

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CDCx706/x906 Termination and Signal Integrity Guidelines (Rev. A)
PDF, 155 Kb, 修订版: A, 档案已发布: Nov 28, 2007
This application report shows and evaluates different schemes for the CDCE706, CDCE906, CDC706, and CDC906. Guidelines for optimizing the series termination are discussed. Additionally, this report describes how the CDCx706/x906 family can be used to drive 1.8-V clock inputs.
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High Speed Layout Guidelines (Rev. A)
PDF, 762 Kb, 修订版: A, 档案已发布: Aug 8, 2017
Thisapplicationreportaddresseshigh-speedsignals,suchas clocksignalsand theirrouting,and givesdesignersa reviewof the importantcoherences.Withsomesimplerules,electromagneticinterferenceproblemscan be minimizedwithoutusingcomplicatedformulasand expensivesimulationtools.Section1givesa shortintroductionto theory,whileSection
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Clock Recommendations for the DM643x EVM
PDF, 121 Kb, 档案已发布: Nov 29, 2006
The DM643x evaluation module (EVM) requires several clock frequencies to run the system properly. The current clocking proposal of the low-cost EVM consists of the VCXO chip PI6CX100-27W, the PLL chip PLL1705, several bus drivers, and a few oscillaors and crystals. This application report discusses several optimized clocking proposals with the Texas Instruments new clock drivers and recommends a m

系列: CDC706 (4)