CDCDLP223
www.ti.com SCAS836 – DECEMBER 2006 3.3 V Clock Synthesizer for DLP™ Systems
FEATURES High-Performance Clock Synthesizer
Uses a 20 MHz Crystal Input to Generate
Multiple Output Frequencies
Integrated Load Capacitance for 20 MHz
Oscillator Reducing System Cost
All PLL Loop Filter Components are
Integrated
Generates the Following Clocks:
– REF CLK 20 MHz (Buffered)
– XCG CLK 100 MHz With SSC
– DMD CLK 200-400 MHz With Selectable
SSC
Very Low Period Jitter Characteristic:
– ±100 ps at 20 MHz Output
– ±75 ps at 100 MHz and 200–400 MHz
Outputs
Includes Spread-Spectrum Clocking (SSC),
With Down Spread for 100 MHz and Center
Spread for 200–400 MHz
HCLK Differential Outputs for the 100 MHz
and the 200–400 MHz Clock …
