Datasheet Texas Instruments CDCE62005 — 数据表
| 制造商 | Texas Instruments |
| 系列 | CDCE62005 |
具有集成双VCO的5/10输出时钟发生器/抖动清除器
数据表
CDCE62005 3:5 Clock Generator, Jitter Cleaner with Integrated Dual VCOs datasheet
PDF, 2.9 Mb, 修订版: G, 档案已发布: May 23, 2016
从文件中提取
价格
状态
| CDCE62005RGZR | CDCE62005RGZT | |
|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | Yes |
打包
| CDCE62005RGZR | CDCE62005RGZT | |
|---|---|---|
| N | 1 | 2 |
| Pin | 48 | 48 |
| Package Type | RGZ | RGZ |
| Industry STD Term | VQFN | VQFN |
| JEDEC Code | S-PQFP-N | S-PQFP-N |
| Package QTY | 2500 | 250 |
| Carrier | LARGE T&R | SMALL T&R |
| Device Marking | 62005 | 62005 |
| Width (mm) | 7 | 7 |
| Length (mm) | 7 | 7 |
| Thickness (mm) | .9 | .9 |
| Pitch (mm) | .5 | .5 |
| Max Height (mm) | 1 | 1 |
| Mechanical Data | 下载 | 下载 |
参数化
| Parameters / Models | CDCE62005RGZR | CDCE62005RGZT |
|---|---|---|
| Input Level | LVPECL, LVDS, LVCMOS | LVPECL, LVDS, LVCMOS |
| Number of Outputs | 5 | 5 |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 |
| Output Frequency(Max), MHz | 1175 | 1175 |
| Output Frequency(Min), MHz | 4.25 | 4.25 |
| Output Level | LVPECL, LVDS, LVCMOS | LVPECL, LVDS, LVCMOS |
| Package Group | VQFN | VQFN |
| Package Size: mm2:W x L, PKG | 48VQFN: 49 mm2: 7 x 7(VQFN) | 48VQFN: 49 mm2: 7 x 7(VQFN) |
| Programmability | EEPROM, SPI | EEPROM, SPI |
| Special Features | Design Tool Available | Design Tool Available |
| VCC Core, V | 3.3 | 3.3 |
| VCC Out, V | 3.3 | 3.3 |
生态计划
| CDCE62005RGZR | CDCE62005RGZT | |
|---|---|---|
| RoHS | Compliant | Compliant |
应用须知
- CDCE62005 Application ReportPDF, 296 Kb, 档案已发布: Nov 21, 2008
- LAN & WAN clock generation and muxing using the CDCE62005PDF, 2.9 Mb, 档案已发布: Nov 19, 2008
- CDCE62005 Phase Noise and Jitter Cleaning PerformancePDF, 2.5 Mb, 档案已发布: Sep 5, 2008
This application report presents phase noise data taken on the Texas Instruments' CDCE62005 jitter cleaner and synchronizer PLL. The phase noise performance of the CDCE62005 depends both on the phase noise of the reference clock and the CDCE62005 itself. This application report shows the phase noise performance at the most popular CDMA frequencies and helps the user to choose the right clocking so - Phase Noise Performance and Loop Bandwidth Optimization of CDCE62005PDF, 556 Kb, 档案已发布: Aug 11, 2011
- Clocking Design Guidelines: Unused PinsPDF, 158 Kb, 档案已发布: Nov 19, 2015
- Effects of Clock Spur on High Speed DAC Performance (Rev. A)PDF, 828 Kb, 修订版: A, 档案已发布: May 18, 2015
- Effects of Clock Noise on High Speed DAC PerformancePDF, 674 Kb, 档案已发布: Nov 8, 2012
- CDCE62005 as Clock Solution for High-Speed ADCsPDF, 805 Kb, 档案已发布: Sep 4, 2008
TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
模型线
系列: CDCE62005 (2)
制造商分类
- Semiconductors> Clock and Timing> Clock Generators> Low Jitter <1psec RMS