Datasheet Texas Instruments CDCE72010 — 数据表

制造商	Texas Instruments
系列	CDCE72010

数据表

价格

状态

打包

参数化

Parameters / Models	CDCE72010RGCR	CDCE72010RGCRG4	CDCE72010RGCT	CDCE72010RGCTG4
Divider Ratio	1 to 80	1 to 80	1 to 80	1 to 80
Input Level	LVCMOS,LVDS,LVPECL	LVCMOS,LVDS,LVPECL	LVCMOS,LVDS,LVPECL	LVCMOS,LVDS,LVPECL
Number of Inputs	2	2	2	2
Number of Outputs	10	10	10	10
Operating Temperature Range, C	-40 to 85	-40 to 85	-40 to 85	-40 to 85
Output Frequency(Max), MHz	1500	1500	1500	1500
Output Frequency(Min), MHz	0.001	0.001	0.001	0.001
Output Level	LVCMOS,LVDS,LVPECL	LVCMOS,LVDS,LVPECL	LVCMOS,LVDS,LVPECL	LVCMOS,LVDS,LVPECL
Package Group	VQFN	VQFN	VQFN	VQFN
Package Size: mm2:W x L, PKG	64VQFN: 81 mm2: 9 x 9(VQFN)	64VQFN: 81 mm2: 9 x 9(VQFN)	64VQFN: 81 mm2: 9 x 9(VQFN)	64VQFN: 81 mm2: 9 x 9(VQFN)
Rating	Catalog	Catalog	Catalog	Catalog
Special Features	Integrated EEPROM,Programmable Phase Offset	Integrated EEPROM,Programmable Phase Offset	Integrated EEPROM,Programmable Phase Offset	Integrated EEPROM,Programmable Phase Offset
Supply Voltage(Max), V	3.6	3.6	3.6	3.6
Supply Voltage(Min), V	3	3	3	3

生态计划

应用须知

• 下载
  Using the CDCE72010 as a Frequency Synthesizer
  PDF, 1.1 Mb, 档案已发布: May 31, 2008
  This application report is a general guide for using the CDCE72010 as a frequency synthesizer. This document explains the methods to work with the phase-locked loop (PLL) of the CDCE72010 to achieve multiple outputfrequencies from any input frequency. It also describes the basic functionality and methods for using the device efficiently. Furthermore, it describes the clock terminationmethod, d
• 下载
  Clock jitter analyzed in the time domain, Part 2
  PDF, 588 Kb, 档案已发布: Nov 15, 2010
• 下载
  Impact of sampling-clock spurs on ADC performance
  PDF, 1.2 Mb, 档案已发布: Jul 14, 2009
• 下载
  Clock jitter analyzed in the time domain, Part 3
  PDF, 627 Kb, 档案已发布: Sep 16, 2011
• 下载
  4Q 2010 Issue Analog Applications Journal
  PDF, 1.3 Mb, 档案已发布: Nov 15, 2010
• 下载
  Q3 2009 Issue Analog Applications Journal
  PDF, 2.1 Mb, 档案已发布: Jul 14, 2009
• 下载
  3Q 2011 Issue Analog Applications Journal
  PDF, 1.4 Mb, 档案已发布: Sep 16, 2011
• 下载
  Журнал по применению аналоговых компонентов 3Q 2011
  PDF, 3.9 Mb, 档案已发布: Sep 1, 2011
• 下载
  Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
  PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
• 下载
  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Kb, 档案已发布: Jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers

模型线

制造商分类

• Semiconductors> Clock and Timing> Clock Jitter Cleaners> Single-Loop PLL