Datasheet Texas Instruments CDCE949 — 数据表

制造商	Texas Instruments
系列	CDCE949

数据表

价格

状态

打包

参数化

Parameters / Models	CDCE949PW	CDCE949PWG4	CDCE949PWR	CDCE949PWRG4
Divider Ratio	Universal	Universal	Universal	Universal
Function	Clock Synthesizer	Clock Synthesizer	Clock Synthesizer	Clock Synthesizer
Input Level	Crystal,LVCMOS	Crystal,LVCMOS	Crystal,LVCMOS	Crystal,LVCMOS
Jitter-Peak to Peak(P-P) or Cycle to Cycle, C-C	60 ps	60 ps	60 ps	60 ps
Number of Outputs	9	9	9	9
Operating Temperature Range, C	-40 to 85	-40 to 85	-40 to 85	-40 to 85
Output Frequency(Max), MHz	230	230	230	230
Output Level	LVCMOS	LVCMOS	LVCMOS	LVCMOS
Output Skew, ps	150	150	150	150
Package Group	TSSOP	TSSOP	TSSOP	TSSOP
Package Size: mm2:W x L, PKG	24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)	24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)	24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)	24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)
Programmability	EEPROM	EEPROM	EEPROM	EEPROM
Rating	Catalog	Catalog	Catalog	Catalog
Special Features	Integrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC)	Integrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC)	Integrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC)	Integrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC)
VCC, V	1.8	1.8	1.8	1.8
VCC Core, V	1.8	1.8	1.8	1.8
VCC Out, V	2.5,3.3	2.5,3.3	2.5,3.3	2.5,3.3

生态计划

应用须知

• 下载
  Clocking Recommendations for DM6446 Digital Video EVM with Sngle PLL (Rev. A)
  PDF, 94 Kb, 修订版: A, 档案已发布: Aug 8, 2007
  The DM6446 (DaVinciв„ў) Digital Video Evaluation Module (EVM) requires a number of clock frequencies to run the system properly. The current clocking proposal of this EVM consists of a VCXO chip PI6CX100-27W, a PLL chip PLL1705, several voltage level translators, and a few oscillators or crystals. This application report discusses an optimized clocking proposal with Texas Instruments new clock driv
• 下载
  General I2C / EEPROM usage for the CDCE(L)9xx family
  PDF, 40 Kb, 档案已发布: Jan 26, 2010
• 下载
  VCXO Application Guideline for CDCE(L)9xx Family (Rev. A)
  PDF, 107 Kb, 修订版: A, 档案已发布: Apr 23, 2012
• 下载
  Practical consideration on choosing a crystal for CDCE(L)9xx family
  PDF, 60 Kb, 档案已发布: Mar 24, 2008
• 下载
  Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913
  PDF, 297 Kb, 档案已发布: Sep 23, 2009
  This document presents a method to smoothly change frequency by IВІCв„ў protocol on Texas Instruments CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 Clock Synthesizers, thus avoiding unnecessary intermediate frequencies. It also includes a code example to generate the IВІC protocol for the CDCE(L)9xx with the TMS320C645x.
• 下载
  Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency
  PDF, 860 Kb, 档案已发布: Mar 31, 2008
  Generating a high-frequency system clock Fs (128fs to 768fs) from a low-frequency sampling clock fs (10 kHz to 200 kHz) is challenging, while attempting to maintain low phase jitter. A traditional phase-lock loop (PLL) can do the frequency translation, but the added phase jitter prevents the generated system clock signal from effectively driving high-performance audio data converters. This applica
• 下载
  Troubleshooting I2C Bus Protocol
  PDF, 184 Kb, 档案已发布: Oct 19, 2009
  When using the I2Cв„ў bus protocol, the designer must ensure that the hardware complies with the I2C standard. This application report describes the I2C protocol and provides guidelines on debugging a missing acknowledgment, selecting the pullup resistors, or meeting the maximum capacitance load of an I2C bus. A conflict occurs if devices sharing the I2C bus have the same slave address. This

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制造商分类

• Semiconductors> Clock and Timing> Clock Generators> Spread-Spectrum Clocks