Datasheet Texas Instruments CDCEL937PWR — 数据表

制造商Texas Instruments
系列CDCEL937
零件号CDCEL937PWR
Datasheet Texas Instruments CDCEL937PWR

具有1.8V LVCMOS输出的可编程3-PLL VCXO时钟合成器20-TSSOP -40至85

数据表

CDCEx937 Flexible Low Power LVCMOS Clock Generator With SSC Support For EMI Reduction datasheet
PDF, 1.2 Mb, 修订版: G, 档案已发布: Oct 10, 2016
从文件中提取

价格

状态

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityYes

打包

Pin20
Package TypePW
Industry STD TermTSSOP
JEDEC CodeR-PDSO-G
Package QTY2000
CarrierLARGE T&R
Device MarkingCDCEL937
Width (mm)4.4
Length (mm)6.5
Thickness (mm)1
Pitch (mm).65
Max Height (mm)1.2
Mechanical Data下载

参数化

Divider RatioUniversal
FunctionClock Synthesizer
Input LevelCrystal,LVCMOS
Jitter-Peak to Peak(P-P) or Cycle to Cycle60 ps C-C
Number of Outputs7
Operating Temperature Range-40 to 85 C
Output Frequency(Max)230 MHz
Output LevelLVCMOS
Output Skew150 ps
Package GroupTSSOP
Package Size: mm2:W x L20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP) PKG
ProgrammabilityEEPROM
RatingCatalog
Special FeaturesIntegrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC)
VCC1.8 V
VCC Core1.8 V
VCC Out1.8 V

生态计划

RoHSCompliant

设计套件和评估模块

  • Evaluation Modules & Boards: CDCEL9XXPROGEVM
    CDCE(L)949 Family EEPROM Programming Board
    Lifecycle Status: Active (Recommended for new designs)

应用须知

  • Practical consideration on choosing a crystal for CDCE(L)9xx family
    PDF, 60 Kb, 档案已发布: Mar 24, 2008
  • Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913
    PDF, 297 Kb, 档案已发布: Sep 23, 2009
    This document presents a method to smoothly change frequency by IВІCв„ў protocol on Texas Instruments CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 Clock Synthesizers, thus avoiding unnecessary intermediate frequencies. It also includes a code example to generate the IВІC protocol for the CDCE(L)9xx with the TMS320C645x.
  • Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency
    PDF, 860 Kb, 档案已发布: Mar 31, 2008
    Generating a high-frequency system clock Fs (128fs to 768fs) from a low-frequency sampling clock fs (10 kHz to 200 kHz) is challenging, while attempting to maintain low phase jitter. A traditional phase-lock loop (PLL) can do the frequency translation, but the added phase jitter prevents the generated system clock signal from effectively driving high-performance audio data converters. This applica
  • Troubleshooting I2C Bus Protocol
    PDF, 184 Kb, 档案已发布: Oct 19, 2009
    When using the I2Cв„ў bus protocol, the designer must ensure that the hardware complies with the I2C standard. This application report describes the I2C protocol and provides guidelines on debugging a missing acknowledgment, selecting the pullup resistors, or meeting the maximum capacitance load of an I2C bus. A conflict occurs if devices sharing the I2C bus have the same slave address. This

模型线

制造商分类

  • Semiconductors > Clock and Timing > Clock Generators > Spread-Spectrum Clocks