Datasheet Texas Instruments CDCEL949PWRG4 — 数据表

制造商	Texas Instruments
系列	CDCEL949
零件号	CDCEL949PWRG4

具有1.8V LVCMOS输出的可编程4-PLL VCXO时钟合成器24-TSSOP -40至85

数据表

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PDF, 1.5 Mb, 修订版: F, 档案已发布: Oct 27, 2016

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价格

状态

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	Yes

打包

Pin	24
Package Type	PW
Industry STD Term	TSSOP
JEDEC Code	R-PDSO-G
Package QTY	2000
Carrier	LARGE T&R
Device Marking	CDCEL949
Width (mm)	4.4
Length (mm)	7.8
Thickness (mm)	1
Pitch (mm)	.65
Max Height (mm)	1.2
Mechanical Data	下载

参数化

Divider Ratio	Universal
Function	Clock Synthesizer
Input Level	Crystal, LVCMOS
Jitter-Peak to Peak(P-P) or Cycle to Cycle	60 ps C-C
Number of Outputs	9
Operating Temperature Range	-40 to 85 C
Output Frequency(Max)	230 MHz
Output Level	LVCMOS
Output Skew	150 ps
Package Group	TSSOP
Package Size: mm2:W x L	24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP) PKG
Programmability	EEPROM
Rating	Catalog
Special Features	Integrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC)
VCC	1.8 V
VCC Core	1.8 V
VCC Out	1.8 V

生态计划

RoHS

Compliant

设计套件和评估模块

Evaluation Modules & Boards: CDCEL949PERF-EVM
CDCEL949 Performance Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
Evaluation Modules & Boards: CDCEL9XXPROGEVM
CDCE(L)949 Family EEPROM Programming Board
Lifecycle Status: Active (Recommended for new designs)

应用须知

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VCXO Application Guideline for CDCE(L)9xx Family (Rev. A)
PDF, 107 Kb, 修订版: A, 档案已发布: Apr 23, 2012
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Practical consideration on choosing a crystal for CDCE(L)9xx family
PDF, 60 Kb, 档案已发布: Mar 24, 2008
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Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913
PDF, 297 Kb, 档案已发布: Sep 23, 2009
This document presents a method to smoothly change frequency by IВІCв„ў protocol on Texas Instruments CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 Clock Synthesizers, thus avoiding unnecessary intermediate frequencies. It also includes a code example to generate the IВІC protocol for the CDCE(L)9xx with the TMS320C645x.
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Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency
PDF, 860 Kb, 档案已发布: Mar 31, 2008
Generating a high-frequency system clock Fs (128fs to 768fs) from a low-frequency sampling clock fs (10 kHz to 200 kHz) is challenging, while attempting to maintain low phase jitter. A traditional phase-lock loop (PLL) can do the frequency translation, but the added phase jitter prevents the generated system clock signal from effectively driving high-performance audio data converters. This applica
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Troubleshooting I2C Bus Protocol
PDF, 184 Kb, 档案已发布: Oct 19, 2009
When using the I2Cв„ў bus protocol, the designer must ensure that the hardware complies with the I2C standard. This application report describes the I2C protocol and provides guidelines on debugging a missing acknowledgment, selecting the pullup resistors, or meeting the maximum capacitance load of an I2C bus. A conflict occurs if devices sharing the I2C bus have the same slave address. This

模型线

系列: CDCEL949 (4)

CDCEL949PW CDCEL949PWG4 CDCEL949PWR CDCEL949PWRG4

制造商分类

Semiconductors > Clock and Timing > Clock Generators > Spread-Spectrum Clocks