Datasheet Texas Instruments CDCF5801DBQRG4 — 数据表

Not Recommended for New Designs CDCF5801
www.ti.com SCAS698F – SEPTEMBER 2003 – REVISED APRIL 2006 CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT
(Not Recommended for New Designs Use CDCF5801A as a Replacement)
FEATURES APPLICATIONS Low-Jitter Clock Multiplier: Г—1, Г—2, Г—4, Г—8
Programmable Bidirectional Delay Steps of
1.3 mUI
Output Frequency Range of 25 MHz to
280 MHz
Input Frequency Range of 12.5 MHz to
240 MHz
Low Jitter Generation
Single-Ended REFCLK Input With Adjustable
Trigger Level (Works With LVTTL, HSTL, and
LVPECL)
Differential/Single-Ended Output
Output Can Drive LVPECL, LVDS, and LVTTL
Three Power Operating Modes to Minimize
Power
Low Power Consumption (< 190 mW at
280 MHz/3.3 V)
Packaged in a Shrink Small-Outline Package
(DBQ)
No External Components Required for PLL …