Datasheet Texas Instruments CDCLVD110VFG4 — 数据表
制造商 | Texas Instruments |
系列 | CDCLVD110 |
零件号 | CDCLVD110VFG4 |
1至10 LVDS时钟缓冲器,最高900MHz,具有最小偏斜,用于时钟分配32-LQFP -40至85
数据表
Programmable Low-Voltage 1:10 LVDS Clock Driver datasheet
PDF, 513 Kb, 修订版: C, 档案已发布: Jan 14, 2008
从文件中提取
价格
状态
Lifecycle Status | NRND (Not recommended for new designs) |
Manufacture's Sample Availability | No |
打包
Pin | 32 |
Package Type | VF |
Industry STD Term | LQFP |
JEDEC Code | S-PQFP-G |
Package QTY | 250 |
Carrier | JEDEC TRAY (10+1) |
Device Marking | CDCLVD110 |
Width (mm) | 7 |
Length (mm) | 7 |
Thickness (mm) | 1.4 |
Pitch (mm) | .8 |
Max Height (mm) | 1.6 |
Mechanical Data | 下载 |
生态计划
RoHS | Compliant |
应用须知
- Benefits of Using TI's Non-PLL Clock Buffer: Best in Class Phase Noise/PhasePDF, 560 Kb, 档案已发布: Jul 18, 2003
This application report presents various jitter and phase noise measurements of three differential clock drivers. A Texas Instruments device was compared to two independent competitor devices. This report proves that clock buffer selection does have an impact on the total system timing budget, particularly when the system has two different input signals connected. Buffers must be able to resist th - DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CMLPDF, 135 Kb, 档案已发布: Feb 19, 2003
- AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)PDF, 417 Kb, 修订版: C, 档案已发布: Oct 17, 2007
This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this reportare low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-modelogic (CML). From these four differential signaling levels, 16
模型线
系列: CDCLVD110 (4)
- CDCLVD110VF CDCLVD110VFG4 CDCLVD110VFR CDCLVD110VFRG4
制造商分类
- Semiconductors > Clock and Timing > Clock Buffers > Differential