Datasheet Texas Instruments CDCLVD1204RGTT — 数据表

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SCAS898B – MAY 2010 – REVISED OCTOBER 2016 CDCLVD1204 2:4 Low Additive Jitter LVDS Buffer
1 Features 3 Description The CDCLVD1204 clock buffer distributes one of two
selectable clock inputs (IN0 and IN1) to 4 pairs of
differential LVDS clock outputs (OUT0 through OUT3)
with minimum skew for clock distribution. The
CDCLVD1204 can accept two clock sources into an
input multiplexer. The inputs can either be LVDS,
LVPECL, or LVCMOS. 1 2:4 Differential Buffer
Low Additive Jitter: 3000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) >1000 UNIT
V Human Body Model, 1.5 kО©, 100 pF
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC Device supply voltage TA Ambient temperature MIN NOM MAX 2.375 2.5 2.625 V 85 °C –40 UNIT 6.4 Thermal Information
CDCLVD1204
THERMAL METRIC (1) RGT (VQFN) UNIT 16 PINS
RОёJA Junction-to-ambient thermal resistance 51.3 В°C/W RОёJC(top) Junction-to-case (top) thermal resistance 85.4 В°C/W RОёJB Junction-to-board thermal resistance 20.1 В°C/W П€JT Junction-to-top characterization parameter 1.3 В°C/W П€JB Junction-to-board characterization parameter 19.4 В°C/W RОёJC(bot) Junction-to-case (bottom) thermal resistance 6 В°C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
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