Datasheet Texas Instruments CDCLVP110MVFRG4 — 数据表

制造商Texas Instruments
系列CDCLVP110
零件号CDCLVP110MVFRG4
Datasheet Texas Instruments CDCLVP110MVFRG4

1:10 LVPECL / HSTL至LVPECL时钟驱动器32-LQFP -40至85

数据表

Low-Voltage 1:10 LVPECL/HSTL With Selectable Input Clock Driver datasheet
PDF, 653 Kb, 修订版: D, 档案已发布: Jan 11, 2011
从文件中提取

价格

状态

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

打包

Pin32
Package TypeVF
Industry STD TermLQFP
JEDEC CodeS-PQFP-G
Package QTY1000
CarrierLARGE T&R
Device MarkingCDCLVP110
Width (mm)7
Length (mm)7
Thickness (mm)1.4
Pitch (mm).8
Max Height (mm)1.6
Mechanical Data下载

参数化

Additive RMS Jitter(Typ)300 fs
Input Frequency(Max)3500 MHz
Input LevelHSTL,LVPECL
Number of Outputs10
Operating Temperature Range-40 to 85 C
Output Frequency(Max)3500 MHz
Output LevelLVPECL
Package GroupLQFP
Package Size: mm2:W x L32LQFP: 81 mm2: 9 x 9(LQFP) PKG
RatingCatalog
VCC2.5,3.3 V
VCC Out2.5,3.3 V

生态计划

RoHSCompliant

应用须知

  • Advantage of Using TI's Lowest Jitter Differential Clock Buffer
    PDF, 221 Kb, 档案已发布: Aug 20, 2003
    Advantage of Using TI's Lowest Jitter Differential Clock Buffer at SONET Speed 622.08 MHz
  • PCB Layout Guidelines for CDCLVP110
    PDF, 70 Kb, 档案已发布: Jun 12, 2002
    This application note describes various electrical and thermal performance considerations for TI's CDCLVP110. In addition, it provides recommendations for PCB layout as well as optimizing power consumption in a real system application. Finally, it shows examples of how to estimate the worst case chip temperature.
  • Clocking Design Guidelines: Unused Pins
    PDF, 158 Kb, 档案已发布: Nov 19, 2015
  • DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML
    PDF, 135 Kb, 档案已发布: Feb 19, 2003
  • AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)
    PDF, 417 Kb, 修订版: C, 档案已发布: Oct 17, 2007
    This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this reportare low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-modelogic (CML). From these four differential signaling levels, 16

模型线

制造商分类

  • Semiconductors > Clock and Timing > Clock Buffers > Differential