Datasheet Texas Instruments CDCLVP110 — 数据表

制造商Texas Instruments
系列CDCLVP110
Datasheet Texas Instruments CDCLVP110

1:10 LVPECL / HSTL至LVPECL时钟驱动器

数据表

Low-Voltage 1:10 LVPECL/HSTL With Selectable Input Clock Driver datasheet
PDF, 653 Kb, 修订版: D, 档案已发布: Jan 11, 2011
从文件中提取

价格

状态

CDCLVP110MVFRCDCLVP110MVFRG4CDCLVP110VFCDCLVP110VFG4CDCLVP110VFRCDCLVP110VFRG4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoYesNoNoYes

打包

CDCLVP110MVFRCDCLVP110MVFRG4CDCLVP110VFCDCLVP110VFG4CDCLVP110VFRCDCLVP110VFRG4
N123456
Pin323232323232
Package TypeVFVFVFVFVFVF
Industry STD TermLQFPLQFPLQFPLQFPLQFPLQFP
JEDEC CodeS-PQFP-GS-PQFP-GS-PQFP-GS-PQFP-GS-PQFP-GS-PQFP-G
Package QTY1000100025025010001000
CarrierLARGE T&RLARGE T&RJEDEC TRAY (10+1)JEDEC TRAY (10+1)LARGE T&RLARGE T&R
Device MarkingCDCLVP110CDCLVP110CDCLVP110CDCLVP110CDCLVP110CDCLVP110
Width (mm)777777
Length (mm)777777
Thickness (mm)1.41.41.41.41.41.4
Pitch (mm).8.8.8.8.8.8
Max Height (mm)1.61.61.61.61.61.6
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参数化

Parameters / ModelsCDCLVP110MVFR
CDCLVP110MVFR
CDCLVP110MVFRG4
CDCLVP110MVFRG4
CDCLVP110VF
CDCLVP110VF
CDCLVP110VFG4
CDCLVP110VFG4
CDCLVP110VFR
CDCLVP110VFR
CDCLVP110VFRG4
CDCLVP110VFRG4
Additive RMS Jitter(Typ), fs300300300300300300
Input Frequency(Max), MHz350035003500350035003500
Input LevelHSTL,LVPECLHSTL,LVPECLHSTL,LVPECLHSTL,LVPECLHSTL,LVPECLHSTL,LVPECL
Number of Outputs101010101010
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Output Frequency(Max), MHz350035003500350035003500
Output LevelLVPECLLVPECLLVPECLLVPECLLVPECLLVPECL
Package GroupLQFPLQFPLQFPLQFPLQFPLQFP
Package Size: mm2:W x L, PKG32LQFP: 81 mm2: 9 x 9(LQFP)32LQFP: 81 mm2: 9 x 9(LQFP)32LQFP: 81 mm2: 9 x 9(LQFP)32LQFP: 81 mm2: 9 x 9(LQFP)32LQFP: 81 mm2: 9 x 9(LQFP)32LQFP: 81 mm2: 9 x 9(LQFP)
RatingCatalogCatalogCatalogCatalogCatalogCatalog
VCC, V2.5,3.32.5,3.32.5,3.32.5,3.32.5,3.32.5,3.3
VCC Out, V2.5,3.32.5,3.32.5,3.32.5,3.32.5,3.32.5,3.3

生态计划

CDCLVP110MVFRCDCLVP110MVFRG4CDCLVP110VFCDCLVP110VFG4CDCLVP110VFRCDCLVP110VFRG4
RoHSCompliantCompliantCompliantCompliantCompliantCompliant

应用须知

  • Advantage of Using TI's Lowest Jitter Differential Clock Buffer
    PDF, 221 Kb, 档案已发布: Aug 20, 2003
    Advantage of Using TI's Lowest Jitter Differential Clock Buffer at SONET Speed 622.08 MHz
  • PCB Layout Guidelines for CDCLVP110
    PDF, 70 Kb, 档案已发布: Jun 12, 2002
    This application note describes various electrical and thermal performance considerations for TI's CDCLVP110. In addition, it provides recommendations for PCB layout as well as optimizing power consumption in a real system application. Finally, it shows examples of how to estimate the worst case chip temperature.
  • Clocking Design Guidelines: Unused Pins
    PDF, 158 Kb, 档案已发布: Nov 19, 2015
  • DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML
    PDF, 135 Kb, 档案已发布: Feb 19, 2003
  • AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)
    PDF, 417 Kb, 修订版: C, 档案已发布: Oct 17, 2007
    This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this reportare low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-modelogic (CML). From these four differential signaling levels, 16

模型线

制造商分类

  • Semiconductors> Clock and Timing> Clock Buffers> Differential