Datasheet Texas Instruments CDCLVP1102RGTT — 数据表

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SCAS884D – AUGUST 2009 – REVISED DECEMBER 2015 CDCLVP1102 Two-LVPECL Output,
High-Performance Clock Buffer
1 Features 3 Description The CDCLVP1102 is a highly versatile, low additive
jitter buffer that can generate two copies of LVPECL
clock outputs from one LVPECL, LVDS, or LVCMOS
input for a variety of communication applications. It
has a maximum clock frequency up to 2 GHz. The
overall additive jitter performance is less than 0.1 ps,
RMS from 10 kHz to 20 MHz, and overall output
skew is as low as 10 ps, making the device a perfect
choice for use in demanding applications. 1 1:2 Differential Buffer
Single Clock Input
Universal Inputs Can Accept LVPECL, LVDS,
LVCMOS/LVTTL
Two LVPECL Outputs
Maximum Clock Frequency: 2 GHz
Maximum Core Current Consumption: 33 mA …