Datasheet Texas Instruments CDCLVP1212RHAT — 数据表

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SCAS886E – AUGUST 2009 – REVISED DECEMBER 2015 CDCLVP1212 LVPECL Output, High-Performance Clock Buffer
1 Features 3 Description The CDCLVP1212 is a highly versatile, low additive
jitter buffer that can generate 12 copies of LVPECL
clock outputs from one of two selectable LVPECL,
LVDS, or LVCMOS inputs for a variety of
communication applications. It has a maximum clock
frequency up to 2 GHz. The CDCLVP1212 features
an on-chip multiplexer (MUX) for selecting one of two
inputs that can be easily configured solely through a
control terminal. The overall additive jitter
performance is less than 0.1 ps, RMS from 10 kHz to
20 MHz, and overall output skew is as low as 25 ps,
making the device a perfect choice for use in
demanding applications. 1 2:12 Differential Buffer
Selectable Clock Inputs Through Control Terminal
Universal Inputs Accept LVPECL, LVDS, and
LVCMOS/LVTTL …