Datasheet Texas Instruments CDCM1804RGER — 数据表

CDCM1804
www.ti.com SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL
LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER S1 VDD0 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 VDD3 (1) VSS(1) 7 8 9 13
10 11 12 Thermal pad must be connected to VSS. P0024-01 S2 VDD0 Y0 Y0 VDD0 S1 24 23 22 21 20 19 RTH PACKAGE
(TOP VIEW) EN 1 18 S0 VDDPECL 2 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 13 VDD3 (1) 7 8 9 10 11 12 VDD2 Y2 Y2 VDD2 Y3 VSS(1) VSS The CDCM1804 has three control terminals, S0, S1,
and S2, to select different output mode settings. The
S[2:0] terminals are 3-level inputs and therefore allow
up to 33 = 27 combinations. Additionally, an enable
terminal (EN) is provided to disable or enable all
outputs simultaneously. The EN terminal is a 3-level
input as well and extends the number of settings to
2 Г— 27 = 54. See Table 1 for details. Y0 2 DESCRIPTION
The CDCM1804 clock driver distributes one pair of
differential clock inputs to three pairs of LVPECL
differential clock outputs Y[2:0] and Y[2:0], with minimum skew for clock distribution. The CDCM1804 is
specifically designed for driving 50-Ω transmission
lines. Additionally, the CDCM1804 offers a
single-ended LVCMOS output Y3. This output is
delayed by 1.6 ns over the three LVPECL output
stages to minimize noise impact during signal transitions. Y0 VDDPECL S0 Y3 24 23 22 21 20 19
18 VDD2 1 Y2 EN Y2 RGE PACKAGE
(TOP VIEW) VDD0 For use in single-ended driver applications, the
CDCM1804 also provides a VBB output terminal that …