Datasheet Texas Instruments CDCM7005-SP — 数据表

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SGLS390G – JULY 2009 – REVISED NOVEMBER 2015 CDCM7005-SP 3.3-V High Performance Rad-Tolerant Class V, Clock Synchronizer and
Jitter Cleaner
1 Features 2 Applications 1 (1) High Performance LVPECL and LVCMOS PLL
Clock Synchronizer
Two Reference Clock Inputs (Primary and
Secondary Clock) for Redundancy Support With
Manual or Automatic Selection
Accepts LVCMOS Input Frequencies Up to
200 MHz
VCXO_IN Clock is Synchronized to One of the
Two Reference Clocks
VCXO_IN Frequencies Up to 2 GHz (LVPECL)
Outputs can be a Combination of LVPECL and
LVCMOS (Up to Five Differential LVPECL Outputs
or Up to 10 LVCMOS Outputs)
Output Frequency is Selectable by x1, /2, /3, /4,
/6, /8, /16 on Each Output Individually …