CDCP1803-EP
www.ti.com. SCAS864 – DECEMBER 2008 1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER
FEATURES 1 S1 VDD0 Y0 Y0 VDD0 24 23 22 21 20 19
18 VDDPECL 2 17 VDD1 IN 3 16 Y1 IN 4 15 Y1 VDDPECL 5 14 VDD1 VBB 6 (2) Thermal VSS(2) 9 13
10 11 12 S0 VSS NC 8 VDD2 7 Y2 1 Y2 EN VDD2 RGE PACKAGE
(TOP VIEW) S2 Distributes One Differential Clock Input to
Three LVPECL Differential Clock Outputs
Programmable Output Divider for Two LVPECL
Outputs
Low-Output Skew 15 ps (Typical)
VCC Range 3 V–3.6 V
Signaling Rate Up to 800-MHz LVPECL
Differential Input Stage for Wide
Common-Mode Range
Provides VBB Bias Voltage Output for
Single-Ended Input Signals
Receiver Input Threshold В±75 mV
24-Terminal QFN Package (4 mm Г— 4 mm)
Accepts Any Differential Signaling:
LVDS, HSTL, CML, VML, SSTL-2, and
Single-Ended: LVTTL/LVCMOS VSS pad must be connected to VSS. P0024-02 SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS (1) Controlled Baseline
One Assembly/Test Site …
