Datasheet Texas Instruments CDCV850IDGGG4 — 数据表
| 制造商 | Texas Instruments |
| 系列 | CDCV850 |
| 零件号 | CDCV850IDGGG4 |
具有2线串行接口的2.5V锁相环差分时钟驱动器48-TSSOP -40至85
数据表
2.5-V Phase Lock Loop Clock Driver With 2-Line Serial Interface datasheet
PDF, 798 Kb, 修订版: D, 档案已发布: Apr 10, 2013
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价格
状态
| Lifecycle Status | NRND (Not recommended for new designs) |
| Manufacture's Sample Availability | No |
打包
| Pin | 48 |
| Package Type | DGG |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 40 |
| Carrier | TUBE |
| Device Marking | CDCV850-I |
| Width (mm) | 6.1 |
| Length (mm) | 12.5 |
| Thickness (mm) | 1.15 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1.2 |
| Mechanical Data | 下载 |
替代品
| Replacement | CDCV850DGG |
| Replacement Code | F |
参数化
| Absolute Jitter (Peak-to-Peak Cycle or Period Jitter) | 30 ps |
| Number of Outputs | 10 |
| Operating Frequency Range(Max) | 140 MHz |
| Operating Frequency Range(Min) | 60 MHz |
| Operating Temperature Range | -40 to 85 C |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP) PKG |
| Rating | Catalog |
| VCC | 2.5 V |
| t(phase error) | 180 ps |
| tsk(o) | 75 ps |
生态计划
| RoHS | Compliant |
应用须知
- HSTL Clock Buffer Using the CDCV850PDF, 35 Kb, 档案已发布: Jul 15, 2002
The demand for driving 1.5-V HSTL signals for high-integrated and low-voltage digital logic is increasing. Most current systems use LVDS, LVPECL, or 2.5-V LVCMOSsignaling levels. Therefore, a solution is needed to convert these clock signals into HSTL signal swing.The purpose this report is to show how to generate an HSTL compliant clock signal using the CDCV850. This clock buffer accepts LV - Using CDC857/CDCV850 toTransform Single-End CLK Signal Into Differential OutputPDF, 437 Kb, 档案已发布: Sep 27, 2000
The CDC857 and the CDCV850 devices are PLL-based differential clock drivers with a maximum operational frequency of 167 MHz. These devices have been designed to support a double-data-rate (DDR) specification and, therefore, they have higher immunity against incoupling common mode noise. However, they require a differential clock input signal.This report shows (a) how to convert a single ended cl
模型线
系列: CDCV850 (6)
- CDCV850DGG CDCV850DGGG4 CDCV850DGGR CDCV850DGGRG4 CDCV850IDGG CDCV850IDGGG4
制造商分类
- Semiconductors > Clock and Timing > Clock Buffers > Zero Delay Buffers