CDCV857A
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS667A – APRIL 2001 – REVISED AUGUST 2002 D
D
D
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D Phase-Lock Loop Clock Driver for Double
Data-Rate Synchronous DRAM
Applications
Spread Spectrum Clock Compatible
Operating Frequency: 60 to 180 MHz
Low Jitter (cyc–cyc): ±50 ps
Distributes One Differential Clock Input to
Ten Differential Outputs D
D
D
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D Three-State Outputs When the Input
Differential Clocks Are 20 MHz input signal this
detection circuit turns on the PLL again and enables the outputs.
When AVDD is strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857A is also able
to track spread spectrum clocking for reduced EMI.
Since the CDCV857A is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. …
