Datasheet Texas Instruments CDCV857B — 数据表
制造商 | Texas Instruments |
系列 | CDCV857B |
2.5 V锁相环DDR时钟驱动器
数据表
CDCV857B, CDCV857BI 2.5-V Phase-Lock Loop Clock Driver datasheet
PDF, 764 Kb, 修订版: A, 档案已发布: Nov 17, 2010
从文件中提取
价格
状态
CDCV857BDGG | CDCV857BDGGG4 | CDCV857BDGGR | CDCV857BDGGRG4 | HPA00014DGG | HPA00014DGGR | |
---|---|---|---|---|---|---|
Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
Manufacture's Sample Availability | Yes | No | Yes | No | Yes | No |
打包
CDCV857BDGG | CDCV857BDGGG4 | CDCV857BDGGR | CDCV857BDGGRG4 | HPA00014DGG | HPA00014DGGR | |
---|---|---|---|---|---|---|
N | 1 | 2 | 3 | 4 | 5 | 6 |
Pin | 48 | 48 | 48 | 48 | 48 | 48 |
Package Type | DGG | DGG | DGG | DGG | DGG | DGG |
Industry STD Term | TSSOP | TSSOP | TSSOP | TSSOP | TSSOP | TSSOP |
JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G |
Package QTY | 40 | 40 | 2000 | 2000 | 40 | 2000 |
Carrier | TUBE | TUBE | LARGE T&R | LARGE T&R | TUBE | LARGE T&R |
Device Marking | CDCV857B | CDCV857B | CDCV857B | CDCV857B | CDCV857B | CDCV857B |
Width (mm) | 6.1 | 6.1 | 6.1 | 6.1 | 6.1 | 6.1 |
Length (mm) | 12.5 | 12.5 | 12.5 | 12.5 | 12.5 | 12.5 |
Thickness (mm) | 1.15 | 1.15 | 1.15 | 1.15 | 1.15 | 1.15 |
Pitch (mm) | .5 | .5 | .5 | .5 | .5 | .5 |
Max Height (mm) | 1.2 | 1.2 | 1.2 | 1.2 | 1.2 | 1.2 |
Mechanical Data | 下载 | 下载 | 下载 | 下载 | 下载 | 下载 |
参数化
Parameters / Models | CDCV857BDGG | CDCV857BDGGG4 | CDCV857BDGGR | CDCV857BDGGRG4 | HPA00014DGG | HPA00014DGGR |
---|---|---|---|---|---|---|
Absolute Jitter (Peak-to-Peak Cycle or Period Jitter), ps | 35 | 35 | 35 | 35 | 35 | 35 |
Number of Outputs | 10 | 10 | 10 | 10 | 10 | 10 |
Operating Frequency Range(Max), MHz | 200 | 200 | 200 | 200 | 200 | 200 |
Operating Frequency Range(Min), MHz | 60 | 60 | 60 | 60 | 60 | 60 |
Operating Temperature Range, C | 0 to 70 | 0 to 70 | 0 to 70 | 0 to 70 | 0 to 70 | 0 to 70 |
Package Group | TSSOP | TSSOP | TSSOP | TSSOP | TSSOP | TSSOP |
Package Size: mm2:W x L, PKG | 48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP) | 48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP) | 48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP) | 48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP) | 48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP) | 48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP) |
Rating | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog |
VCC, V | 2.5 | 2.5 | 2.5 | 2.5 | 2.5 | 2.5 |
t(phase error), ps | 100 | 100 | 100 | 100 | 100 | 100 |
tsk(o), ps | 100 | 100 | 100 | 100 | 100 | 100 |
生态计划
CDCV857BDGG | CDCV857BDGGG4 | CDCV857BDGGR | CDCV857BDGGRG4 | HPA00014DGG | HPA00014DGGR | |
---|---|---|---|---|---|---|
RoHS | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant |
模型线
系列: CDCV857B (6)
制造商分类
- Semiconductors> Clock and Timing> Clock Buffers> Zero Delay Buffers