Datasheet Texas Instruments CDCVF111 — 数据表

制造商	Texas Instruments
系列	CDCVF111

数据表

价格

状态

打包

参数化

Parameters / Models	CDCVF111FN	CDCVF111FNG4	CDCVF111FNR	CDCVF111FNRG4
Input Frequency(Max), MHz	650	650	650	650
Input Level	LVPECL	LVPECL	LVPECL	LVPECL
Number of Outputs	9	9	9	9
Operating Temperature Range, C	-40 to 85	-40 to 85	-40 to 85	-40 to 85
Output Frequency(Max), MHz	650	650	650	650
Output Level	LVPECL	LVPECL	LVPECL	LVPECL
Package Group	PLCC	PLCC	PLCC	PLCC
Package Size: mm2:W x L, PKG	28PLCC: 132 mm2: 11.51 x 11.51(PLCC)	28PLCC: 132 mm2: 11.51 x 11.51(PLCC)	28PLCC: 132 mm2: 11.51 x 11.51(PLCC)	28PLCC: 132 mm2: 11.51 x 11.51(PLCC)
Rating	Catalog	Catalog	Catalog	Catalog
VCC, V	3.3	3.3	3.3	3.3
VCC Out, V	3.3	3.3	3.3	3.3

生态计划

应用须知

• 下载
  Using TI's CDC111 W/SLK2501 Serial Gigabit Transceiver for SONET, Ethernet
  PDF, 72 Kb, 档案已发布: Oct 31, 2001
  SONET/SDH and gigabit ethernet applications all have stringent timing requirements, which mandate the use of low-skew, low-jitter clock distribution. Texas Instruments has developed two products targeting these systems applications. The first product is the CDCVF111, a 1:9 low-skew, low-jitter differential LVPECL clock driver. The second is the SLK2501, a multirate (OC-48/24/12/3) serial gigabit t
• 下载
  Using TI's CDC111/CDCVF111 W/ TLK3104SA Serial Transceiver for Gigabit Ethernet
  PDF, 79 Kb, 档案已发布: Oct 31, 2001
  This application report discusses jitter transfer of TI's CDC111/CDCVF111 clock drivers when driving TI's TLK3104 serial gigabit transceiver. This report summarizes worst case peak-to-peak and RMS jitter measurements taken at various points, as indicated in Figures 1 and 2. Two different clock sources are used to provide the reference clock signal for the clock drivers, and the output of each cloc
• 下载
  Jitter Performance of TI's CDC111/CDCVF111
  PDF, 149 Kb, 档案已发布: Oct 29, 2001
  This application report discusses various jitter measurements of TI?s CDC111/CDCVF111 while being driven by three different clock sources (VCXOs). The data contained in this report shows that the CDC111/CDCVF111 does not add more than 3 ps of peak-to-peak jitter. Hence, the CDC111 and CDCVF111 are ideal for various SONET and Gigabit Ethernet applications where skew and jitter are of major concern.
• 下载
  Output Jitter of CDC111/CDCVF111 in ASIC Networking Application
  PDF, 361 Kb, 档案已发布: Nov 2, 2001
  This report contains a number of peak-to-peak and cycle-to-cycle jitter measurements of TI?s CDC111 and CDCVF111 clock driver. In this ASIC event, both the CDC111/CDCVF111 clock drivers are used as a master clock distribution for the Gandalf Macro Family Testchip. Comprehensive jitter data as well as output signal levels were taken and thus are included for completeness.
• 下载
  DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML
  PDF, 135 Kb, 档案已发布: Feb 19, 2003
• 下载
  AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)
  PDF, 417 Kb, 修订版: C, 档案已发布: Oct 17, 2007
  This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this reportare low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-modelogic (CML). From these four differential signaling levels, 16

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制造商分类

• Semiconductors> Clock and Timing> Clock Buffers> Differential