CDCVF855
www.ti.com SCAS839A – APRIL 2007 – REVISED MAY 2007 2.5-V PHASE-LOCKED-LOOP CLOCK DRIVER
FEATURES DESCRIPTION Spread-Spectrum Clock Compatible
Operating Frequency: 60 MHz to 220 MHz
Low Jitter (Cycle-Cycle): В±60 ps (В±40 ps at 200
MHz)
Low Static Phase Offset: В±50 ps
Low Jitter (Period): В±60 ps (В±30 ps at 200 MHz)
1-to-4 Differential Clock Distribution (SSTL2)
Best in Class for VOX = VDD/2 В±0.1 V
Operates From Dual 2.6-V or 2.5-V Supplies
Available in a 28-Pin TSSOP Package
Consumes < 100-ВµA Quiescent Current
External Feedback Pins (FBIN, FBIN) Are Used
to Synchronize the Outputs to the Input
Clocks
Meets/Exceeds JEDEC Standard (JESD82-1)
For DDRI-200/266/333 Specification
Meets/Exceeds Proposed DDRI-400
Specification (JESD82-1A)
Enters Low-Power Mode When No CLK Input
Signal Is Applied or PWRDWN Is Low APPLICATIONS DDR Memory Modules (DDR400/333/266/200)
Zero-Delay Fan-Out Buffer The CDCVF855 is a high-performance, low-skew, …
