CDCVF857
www.ti.com SCAS047F – MARCH 2003 – REVISED MAY 2007 2.5-V PHASE-LOCKED-LOOP CLOCK DRIVER
FEATURES DESCRIPTION Spread-Spectrum Clock Compatible
Operating Frequency: 60 MHz to 220 MHz
Low Jitter (Cycle-Cycle): В±35 ps
Low Static Phase Offset: В±50 ps
Low Jitter (Period): В±30 ps
1-to-10 Differential Clock Distribution (SSTL2)
Best in Class for VOX = VDD/2 В±0.1 V
Operates From Dual 2.6-V or 2.5-V Supplies
Available in a 40-Pin MLF Package, 48-Pin
TSSOP Package, 56-Ball MicroStar Juniorв„ў
BGA Package
Consumes < 100-ВµA Quiescent Current
External Feedback Pins (FBIN, FBIN) Are Used
to Synchronize the Outputs to the Input
Clocks
Meets/Exceeds JEDEC Standard (JESD82-1)
For DDRI-200/266/333 Specification
Meets/Exceeds Proposed DDRI-400
Specification (JESD82-1A)
Enters Low-Power Mode When No CLK Input
Signal Is Applied or PWRDWN Is Low The CDCVF857 is a high-performance, low-skew, …
