Datasheet Texas Instruments DAC2902 — 数据表
| 制造商 | Texas Instruments |
| 系列 | DAC2902 |
双通道，12位，125MSPS数模转换器（DAC）
数据表
Dual, 12-Bit, 125MSPS Digital-to-Analog Converter (Rev. C)
PDF, 990 Kb, 修订版: C, 档案已发布: Sep 19, 2008
Dual, 12-Bit, 125MSPS Digital-to-Analog Converter datasheet
PDF, 991 Kb, 修订版: C, 档案已发布: Sep 19, 2008
从文件中提取
价格
状态
| DAC2902Y/1K | DAC2902Y/1KG4 | DAC2902Y/250 | |
|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | No | No |
打包
| DAC2902Y/1K | DAC2902Y/1KG4 | DAC2902Y/250 | |
|---|---|---|---|
| N | 1 | 2 | 3 |
| Pin | 48 | 48 | 48 |
| Package Type | PFB | PFB | PFB |
| Industry STD Term | TQFP | TQFP | TQFP |
| JEDEC Code | S-PQFP-G | S-PQFP-G | S-PQFP-G |
| Package QTY | 1000 | 1000 | 250 |
| Carrier | LARGE T&R | LARGE T&R | SMALL T&R |
| Device Marking | DAC2902Y | DAC2902Y | DAC2902Y |
| Width (mm) | 7 | 7 | 7 |
| Length (mm) | 7 | 7 | 7 |
| Thickness (mm) | 1 | 1 | 1 |
| Pitch (mm) | .5 | .5 | .5 |
| Max Height (mm) | 1.2 | 1.2 | 1.2 |
| Mechanical Data | 下载 | 下载 | 下载 |
参数化
| Parameters / Models | DAC2902Y/1K | DAC2902Y/1KG4 | DAC2902Y/250 |
|---|---|---|---|
| Approx. Price (US$) | 17.23 | 1ku | ||
| Architecture | Current Source | Current Source | Current Source |
| DAC Channels | 2 | 2 | |
| DAC: Channels | 2 | ||
| Interface | Parallel CMOS | Parallel CMOS | Parallel CMOS |
| Interpolation | 1x | 1x | |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 | |
| Operating Temperature Range(C) | -40 to 85 | ||
| Package Group | TQFP | TQFP | TQFP |
| Package Size(mm2=WxL) | 48TQFP: 81 mm2: 9 x 9 | ||
| Package Size: mm2:W x L, PKG | 48TQFP: 81 mm2: 9 x 9(TQFP) | 48TQFP: 81 mm2: 9 x 9(TQFP) | |
| Power Consumption(Typ), mW | 310 | 310 | |
| Power Consumption(Typ)(mW) | 310 | ||
| Rating | Catalog | Catalog | Catalog |
| Resolution, Bits | 12 | 12 | |
| Resolution(Bits) | 12 | ||
| SFDR, dB | 80 | 80 | |
| SFDR(dB) | 81 | ||
| SNR(dB) | 68 | ||
| Sample / Update Rate, MSPS | 125 | 125 | |
| Sample / Update Rate(MSPS) | 125 | ||
| Settling Time(?s) | 0.03 |
生态计划
| DAC2902Y/1K | DAC2902Y/1KG4 | DAC2902Y/250 | |
|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant |
| Pb Free | Yes |
应用须知
- Interfacing op amps to high-speed DACs, Part 2: Current-sourcing DACsPDF, 617 Kb, 档案已发布: Oct 4, 2009
- Q4 2009 Issue Analog Applications JournalPDF, 1.5 Mb, 档案已发布: Oct 4, 2009
- Wideband Complementary Current Output DAC Single-Ended InterfacePDF, 597 Kb, 档案已发布: Jun 21, 2005
High-speed digital-to-analog converters (DACs) most often use a transformer-coupled output stage. In applications where this configuration is not practical, a single op amp differential to single-end - Superposition: The Hidden DAC Linearity ErrorPDF, 106 Kb, 档案已发布: Oct 2, 2000
A digital-to analog converter (DAC) translates digital signals to analog signals. For example, a 12-bit DAC takes a 12-bit binary number, called an input code, and converts it into one of 4,096 analog - Interfacing op amps to high-speed DACs, Part 2: Current-sourcing DACsPDF, 617 Kb, 档案已发布: Oct 4, 2009
- Q4 2009 Issue Analog Applications JournalPDF, 1.5 Mb, 档案已发布: Oct 4, 2009
- Wideband Complementary Current Output DAC Single-Ended InterfacePDF, 597 Kb, 档案已发布: Jun 21, 2005
High-speed digital-to-analog converters (DACs) most often use a transformer-coupled output stage. In applications where this configuration is not practical, a single op ampdifferential to single-ended stage has often been used. This application note steps through the exact design equations required to achieve gain matching from each output as well as a matched input impedance to each of the DA
模型线
系列: DAC2902 (3)
制造商分类
- Semiconductors> Data Converters> Digital-to-Analog Converters (DACs)> High Speed DACs (>10MSPS)