Datasheet Texas Instruments DAC5662 — 数据表
| 制造商 | Texas Instruments |
| 系列 | DAC5662 |
双通道，12位，275MSPS数模转换器（DAC）
数据表
Dual, 12-Bit, 275 MSPS Digital-to-Analog Converter (Rev. B)
PDF, 728 Kb, 修订版: B, 档案已发布: May 14, 2009
Dual, 12-Bit, 275 MSPS Digital-to-Analog Converter datasheet
PDF, 725 Kb, 修订版: B, 档案已发布: May 14, 2009
从文件中提取
价格
状态
| DAC5662IPFB | DAC5662IPFBR | DAC5662IPFBRG4 | |
|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | No | Yes |
打包
| DAC5662IPFB | DAC5662IPFBR | DAC5662IPFBRG4 | |
|---|---|---|---|
| N | 1 | 2 | 3 |
| Pin | 48 | 48 | 48 |
| Package Type | PFB | PFB | PFB |
| Industry STD Term | TQFP | TQFP | TQFP |
| JEDEC Code | S-PQFP-G | S-PQFP-G | S-PQFP-G |
| Package QTY | 250 | 1000 | 1000 |
| Carrier | JEDEC TRAY (10+1) | LARGE T&R | LARGE T&R |
| Device Marking | DAC5662I | DAC5662I | DAC5662I |
| Width (mm) | 7 | 7 | 7 |
| Length (mm) | 7 | 7 | 7 |
| Thickness (mm) | 1 | 1 | 1 |
| Pitch (mm) | .5 | .5 | .5 |
| Max Height (mm) | 1.2 | 1.2 | 1.2 |
| Mechanical Data | 下载 | 下载 | 下载 |
参数化
| Parameters / Models | DAC5662IPFB | DAC5662IPFBR | DAC5662IPFBRG4 |
|---|---|---|---|
| Approx. Price (US$) | 11.25 | 1ku | ||
| Architecture | Current Source | Current Source | Current Source |
| DAC Channels | 2 | 2 | |
| DAC: Channels | 2 | ||
| IMD3(dBc) | 78 | ||
| Interface | Parallel CMOS | Parallel CMOS | Parallel CMOS |
| Interpolation | 1x | 1x | |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 | |
| Operating Temperature Range(C) | -40 to 85 | ||
| Package Group | TQFP | TQFP | TQFP |
| Package Size(mm2=WxL) | 48TQFP: 81 mm2: 9 x 9 | ||
| Package Size: mm2:W x L, PKG | 48TQFP: 81 mm2: 9 x 9(TQFP) | 48TQFP: 81 mm2: 9 x 9(TQFP) | |
| Power Consumption(Typ), mW | 330 | 330 | |
| Power Consumption(Typ)(mW) | 330 | ||
| Rating | Catalog | Catalog | Catalog |
| Resolution, Bits | 12 | 12 | |
| Resolution(Bits) | 12 | ||
| SFDR, dB | 81 | 81 | |
| SFDR(dB) | 81 | ||
| SNR(dB) | 73 | ||
| Sample / Update Rate, MSPS | 275 | 275 | |
| Sample / Update Rate(MSPS) | 275 | ||
| Settling Time(?s) | 0.02 |
生态计划
| DAC5662IPFB | DAC5662IPFBR | DAC5662IPFBRG4 | |
|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant |
| Pb Free | Yes |
应用须知
- Interfacing op amps to high-speed DACs, Part 2: Current-sourcing DACsPDF, 617 Kb, 档案已发布: Oct 4, 2009
- Passive Terminations for Current Output DACsPDF, 244 Kb, 档案已发布: Nov 10, 2008
The correct implementation of the high-speed DAC output termination is critical to achieving the best possible performance. The typical application involves choosing the correct network to create the necessary dc bias levels and correct effective impedance load to keep the output voltage within the compliance levels. This ensures that the maximum output signal amplitude and optimum ac performance - High Speed Digital-to-Analog Converters Basics (Rev. A)PDF, 829 Kb, 修订版: A, 档案已发布: Oct 23, 2012
- Q4 2009 Issue Analog Applications JournalPDF, 1.5 Mb, 档案已发布: Oct 4, 2009
- Wideband Complementary Current Output DAC Single-Ended InterfacePDF, 597 Kb, 档案已发布: Jun 21, 2005
High-speed digital-to-analog converters (DACs) most often use a transformer-coupled output stage. In applications where this configuration is not practical, a single op ampdifferential to single-ended stage has often been used. This application note steps through the exact design equations required to achieve gain matching from each output as well as a matched input impedance to each of the DA
模型线
系列: DAC5662 (3)
制造商分类
- Semiconductors> Data Converters> Digital-to-Analog Converters (DACs)> High Speed DACs (>10MSPS)