Datasheet Texas Instruments DAC5682Z — 数据表

制造商	Texas Instruments
系列	DAC5682Z

数据表

价格

状态

打包

参数化

Parameters / Models	DAC5682ZIRGC	DAC5682ZIRGCR	DAC5682ZIRGCT
Architecture	Current Sink	Current Sink	Current Sink
DAC Channels	2	2	2
Interface	Parallel LVDS	Parallel LVDS	Parallel LVDS
Interpolation	1x,2x,4x	1x,2x,4x	1x,2x,4x
Operating Temperature Range, C	-40 to 85	-40 to 85	-40 to 85
Package Group	VQFN	VQFN	VQFN
Package Size: mm2:W x L, PKG	64VQFN: 81 mm2: 9 x 9(VQFN)	64VQFN: 81 mm2: 9 x 9(VQFN)	64VQFN: 81 mm2: 9 x 9(VQFN)
Power Consumption(Typ), mW	1300	1300	1300
Rating	Catalog	Catalog	Catalog
Resolution, Bits	16	16	16
SFDR, dB	81	81	81
Sample / Update Rate, MSPS	1000	1000	1000

生态计划

应用须知

• 下载
  Design of Differential Filters for High-Speed Signal Chains (Rev. B)
  PDF, 166 Kb, 修订版: B, 档案已发布: Apr 30, 2010
  Differential filters have many desirable attributes. The task of designing differential filters can seem daunting at first. Single-ended filters designed in any filter design package can be converted to a differential implementation. This application report explores simple conversion techniques for low-pass, high-pass, and band-pass LC filters.
• 下载
  Interfacing op amps to high-speed DACs, Part 1: Current-sinking DACs
  PDF, 319 Kb, 档案已发布: Jul 14, 2009
• 下载
  Passive Terminations for Current Output DACs
  PDF, 244 Kb, 档案已发布: Nov 10, 2008
  The correct implementation of the high-speed DAC output termination is critical to achieving the best possible performance. The typical application involves choosing the correct network to create the necessary dc bias levels and correct effective impedance load to keep the output voltage within the compliance levels. This ensures that the maximum output signal amplitude and optimum ac performance
• 下载
  Q3 2009 Issue Analog Applications Journal
  PDF, 2.1 Mb, 档案已发布: Jul 14, 2009
• 下载
  High Speed Digital-to-Analog Converters Basics (Rev. A)
  PDF, 829 Kb, 修订版: A, 档案已发布: Oct 23, 2012
• 下载
  Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
  PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
• 下载
  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Kb, 档案已发布: Jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers

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制造商分类

• Semiconductors> Data Converters> Digital-to-Analog Converters (DACs)> High Speed DACs (>10MSPS)