Datasheet Texas Instruments DAC5687 — 数据表
| 制造商 | Texas Instruments |
| 系列 | DAC5687 |
双通道，16位，500MSPS，1x-8x内插数模转换器（DAC）
数据表
16-Bit 500 MSPS 2x-8x Interpolating Dual-Channel DAC datasheet
PDF, 2.7 Mb, 修订版: E, 档案已发布: Sep 20, 2006
从文件中提取
价格
状态
| DAC5687IPZP | DAC5687IPZPG4 | DAC5687IPZPR | |
|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes | No | Yes |
打包
| DAC5687IPZP | DAC5687IPZPG4 | DAC5687IPZPR | |
|---|---|---|---|
| N | 1 | 2 | 3 |
| Pin | 100 | 100 | 100 |
| Package Type | PZP | PZP | PZP |
| Industry STD Term | HTQFP | HTQFP | HTQFP |
| JEDEC Code | S-PQFP-G | S-PQFP-G | S-PQFP-G |
| Package QTY | 90 | 90 | 1000 |
| Carrier | EIAJ TRAY (10+1) | EIAJ TRAY (10+1) | LARGE T&R |
| Device Marking | DAC5687IPZP | DAC5687IPZP | DAC5687IPZP |
| Width (mm) | 14 | 14 | 14 |
| Length (mm) | 14 | 14 | 14 |
| Thickness (mm) | 1 | 1 | 1 |
| Pitch (mm) | .5 | .5 | .5 |
| Max Height (mm) | 1.2 | 1.2 | 1.2 |
| Mechanical Data | 下载 | 下载 | 下载 |
参数化
| Parameters / Models | DAC5687IPZP | DAC5687IPZPG4 | DAC5687IPZPR |
|---|---|---|---|
| Architecture | Current Sink | Current Sink | Current Sink |
| DAC Channels | 2 | 2 | 2 |
| Interface | Parallel CMOS | Parallel CMOS | Parallel CMOS |
| Interpolation | 1x,2x,4x,8x | 1x,2x,4x,8x | 1x,2x,4x,8x |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 | -40 to 85 |
| Package Group | HTQFP | HTQFP | HTQFP |
| Package Size: mm2:W x L, PKG | 100HTQFP: 256 mm2: 16 x 16(HTQFP) | 100HTQFP: 256 mm2: 16 x 16(HTQFP) | 100HTQFP: 256 mm2: 16 x 16(HTQFP) |
| Power Consumption(Typ), mW | 1410 | 1410 | 1410 |
| Rating | Catalog | Catalog | Catalog |
| Resolution, Bits | 16 | 16 | 16 |
| SFDR, dB | 80 | 80 | 80 |
| Sample / Update Rate, MSPS | 500 | 500 | 500 |
生态计划
| DAC5687IPZP | DAC5687IPZPG4 | DAC5687IPZPR | |
|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant |
应用须知
- DAC5686/DAC5687 Clock Generation Using PLL & External Clock Modes (Rev. A)PDF, 686 Kb, 修订版: A, 档案已发布: Jul 21, 2005
DAC5686/DAC5687 Application NOte Clock Generation Using PLL & External Clock Modes - Interfacing op amps to high-speed DACs, Part 1: Current-sinking DACsPDF, 319 Kb, 档案已发布: Jul 14, 2009
- Passive Terminations for Current Output DACsPDF, 244 Kb, 档案已发布: Nov 10, 2008
The correct implementation of the high-speed DAC output termination is critical to achieving the best possible performance. The typical application involves choosing the correct network to create the necessary dc bias levels and correct effective impedance load to keep the output voltage within the compliance levels. This ensures that the maximum output signal amplitude and optimum ac performance - Q3 2009 Issue Analog Applications JournalPDF, 2.1 Mb, 档案已发布: Jul 14, 2009
- High Speed Digital-to-Analog Converters Basics (Rev. A)PDF, 829 Kb, 修订版: A, 档案已发布: Oct 23, 2012
- Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, 档案已发布: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
模型线
系列: DAC5687 (3)
制造商分类
- Semiconductors> Data Converters> Digital-to-Analog Converters (DACs)> High Speed DACs (>10MSPS)