Datasheet Texas Instruments DAC5688 — 数据表

制造商	Texas Instruments
系列	DAC5688

数据表

价格

状态

打包

参数化

Parameters / Models	DAC5688IRGCR	DAC5688IRGCRG4	DAC5688IRGCT
Architecture	Current Sink	Current Sink	Current Sink
DAC Channels	2	2	2
Interface	Parallel CMOS	Parallel CMOS	Parallel CMOS
Interpolation	1x,2x,4x,8x	1x,2x,4x,8x	1x,2x,4x,8x
Operating Temperature Range, C	-40 to 85	-40 to 85	-40 to 85
Package Group	VQFN	VQFN	VQFN
Package Size: mm2:W x L, PKG	64VQFN: 81 mm2: 9 x 9(VQFN)	64VQFN: 81 mm2: 9 x 9(VQFN)	64VQFN: 81 mm2: 9 x 9(VQFN)
Power Consumption(Typ), mW	1750	1750	1750
Rating	Catalog	Catalog	Catalog
Resolution, Bits	16	16	16
SFDR, dB	80	80	80
Sample / Update Rate, MSPS	800	800	800

生态计划

应用须知

• 下载
  Interfacing op amps to high-speed DACs, Part 1: Current-sinking DACs
  PDF, 319 Kb, 档案已发布: Jul 14, 2009
• 下载
  Passive Terminations for Current Output DACs
  PDF, 244 Kb, 档案已发布: Nov 10, 2008
  The correct implementation of the high-speed DAC output termination is critical to achieving the best possible performance. The typical application involves choosing the correct network to create the necessary dc bias levels and correct effective impedance load to keep the output voltage within the compliance levels. This ensures that the maximum output signal amplitude and optimum ac performance
• 下载
  Q3 2009 Issue Analog Applications Journal
  PDF, 2.1 Mb, 档案已发布: Jul 14, 2009
• 下载
  Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
  PDF, 376 Kb, 档案已发布: Apr 28, 2009
  This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
• 下载
  Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
  PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
• 下载
  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Kb, 档案已发布: Jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers

模型线

制造商分类

• Semiconductors> Data Converters> Digital-to-Analog Converters (DACs)> High Speed DACs (>10MSPS)