Datasheet Texas Instruments DS25BR120 — 数据表

制造商Texas Instruments
系列DS25BR120
Datasheet Texas Instruments DS25BR120

具有发送预加重的3.125 Gbps LVDS缓冲器

数据表

DS25BR120 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis datasheet
PDF, 841 Kb, 修订版: E, 档案已发布: Apr 14, 2013
从文件中提取

价格

状态

DS25BR120TSD/NOPB
Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityYes

打包

DS25BR120TSD/NOPB
N1
Pin8
Package TypeNGQ
Industry STD TermWSON
JEDEC CodeS-PDSO-N
Package QTY1000
CarrierSMALL T&R
Device Marking2R120
Width (mm)3
Length (mm)3
Thickness (mm).8
Pitch (mm).5
Max Height (mm).8
Mechanical Data下载

参数化

Parameters / ModelsDS25BR120TSD/NOPB
DS25BR120TSD/NOPB
Device TypeBuffer
ESD HBM, kV7
FunctionBuffer
ICC(Max), mA43
Operating Temperature Range, C-40 to 85
Package GroupWSON
Package Size: mm2:W x L, PKGSee datasheet (WSON)
ProtocolsLVDS

生态计划

DS25BR120TSD/NOPB
RoHSCompliant

应用须知

  • LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A)
    PDF, 101 Kb, 修订版: A, 档案已发布: Apr 29, 2013
    This application note introduces Texas Instrument’s LVDS devices with built-in pre-emphasis andequalization circuits, recommends when it makes sense to employ them with the FPD-Link II SER/DES,shows how to optimally interface them to the SER/DES, and discusses distance gains that may berealized with their signal enhancing functions.
  • AN-1957 LVDS Signal Conditioners Reduce Data-Dependent Jitter (Rev. A)
    PDF, 275 Kb, 修订版: A, 档案已发布: Apr 26, 2013
    Jitter is a phenomenon troubling many designers of high-speed interfaces. It reduces available timingmargin, limits transmission distance between a transmitter and a receiver, and increases system cost bydemanding better performing and more expensive interconnects. LVDS interfaces are not spared fromthese ill effects as they now operate at bit rates exceeding the 3 Gbps mark. Texas Instrumen

模型线

系列: DS25BR120 (1)

制造商分类

  • Semiconductors> Interface> Signal Conditioners> Buffer