Datasheet Texas Instruments DS32EL0124 — 数据表
| 制造商 | Texas Instruments |
| 系列 | DS32EL0124 |
具有DDR LVDS并行接口的125 MHz-312.5 MHz FPGA-Link解串器
数据表
DS32EL0124/ELX0124 125MHz-312.5MHz FPGA-Link Deserializr w/DDR LVDS Para I/F datasheet
PDF, 2.6 Mb, 修订版: K, 档案已发布: Apr 15, 2013
从文件中提取
价格
状态
| DS32EL0124SQ/NOPB | DS32EL0124SQE/NOPB | DS32EL0124SQX/NOPB | |
|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | Yes | No |
打包
| DS32EL0124SQ/NOPB | DS32EL0124SQE/NOPB | DS32EL0124SQX/NOPB | |
|---|---|---|---|
| N | 1 | 2 | 3 |
| Pin | 48 | 48 | 48 |
| Package Type | RHS | RHS | RHS |
| Industry STD Term | WQFN | WQFN | WQFN |
| JEDEC Code | S-PQFP-N | S-PQFP-N | S-PQFP-N |
| Package QTY | 1000 | 250 | 2500 |
| Carrier | LARGE T&R | SMALL T&R | LARGE T&R |
| Device Marking | 32EL0124 | 32EL0124 | 32EL0124 |
| Width (mm) | 7 | 7 | 7 |
| Length (mm) | 7 | 7 | 7 |
| Thickness (mm) | .75 | .75 | .75 |
| Pitch (mm) | .5 | .5 | .5 |
| Max Height (mm) | .8 | .8 | .8 |
| Mechanical Data | 下载 | 下载 | 下载 |
参数化
| Parameters / Models | DS32EL0124SQ/NOPB | DS32EL0124SQE/NOPB | DS32EL0124SQX/NOPB |
|---|---|---|---|
| Operating Temperature Range, C | -40 to 85 | -40 to 85 | -40 to 85 |
| Package Group | WQFN | WQFN | WQFN |
| Package Size: mm2:W x L, PKG | 48WQFN: 49 mm2: 7 x 7(WQFN) | 48WQFN: 49 mm2: 7 x 7(WQFN) | 48WQFN: 49 mm2: 7 x 7(WQFN) |
| Rating | Catalog | Catalog | Catalog |
生态计划
| DS32EL0124SQ/NOPB | DS32EL0124SQE/NOPB | DS32EL0124SQX/NOPB | |
|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant |
应用须知
- Expanding the Payload w/FPGA-Link DS32ELX0421 and DS32ELX0124 SER/DES (Rev. A)PDF, 60 Kb, 修订版: A, 档案已发布: Apr 26, 2013
High data payload, reaching across 10’s of meters of low cost media, is stretching the current boundariesof high speed transceiver solutions.Whether the data is packetized for fiber channel at 4.25 Gbps or twostreams of HD video content are multiplexed in a single link, more markets are emerging to push the limitsof current high speed data solutions. - LVDS Timing DS32ELX0421 and DS32ELX0124 Serializers and Deserializers (Rev. A)PDF, 55 Kb, 修订版: A, 档案已发布: Apr 26, 2013
The highly integrated FPGA-Link SerDes chipset (DS32ELX0421 and DS32ELX0124) enables low-costFPGAs in a variety of high performance, high-speed applications. They feature advanced on-chip signaland clock conditioning circuitry that extends the data transmission reach of CAT-6 (shielded 24 AWG)cable beyond 20 meters without additional external components.
模型线
系列: DS32EL0124 (3)
制造商分类
- Semiconductors> Interface> Serializer, Deserializer> FPGA-Link