Datasheet Texas Instruments DS90CF386SLCX/NOPB — 数据表

+ 3.3V LVDS接收器24位平板显示（FPD）链接-85 MHz 64-NFBGA -10至70

数据表

PDF, 2.2 Mb, 修订版: J, 档案已发布: May 31, 2016

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Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

Color Depth	24 bpp
Function	Receiver
Input Compatibility	FPD-Link LVDS
Operating Temperature Range	-10 to 70 C
Output Compatibility	LVCMOS
Package Group	NFBGA
Package Size: mm2:W x L	64NFBGA: 64 mm2: 8 x 8(NFBGA) PKG
Pixel Clock Min	20 MHz
Pixel Clock(Max)	85 MHz
Rating	Catalog
Total Throughput	2380 Mbps

RoHS

Compliant

Evaluation Modules & Boards: FLINK3V8BT-85
Evaluation Kit for FPD-Link Family of Serializer and Deserializer LVDS Devices
Lifecycle Status: Active (Recommended for new designs)
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AN-1056 STN Application Using FPD-Link
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Application Note 1056 STN Application Using FPD-Link
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TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map
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Application Note 1163 TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map
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LVDS Display Interface (LDI) TFT Data Mapping for Interoperability w/FPD-Link
PDF, 65 Kb, 档案已发布: May 14, 2004
Application Note 1127 LVDS Display Interface (LDI) TFT Data Mapping for Interoperabil ity with FPD-Link
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AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines
PDF, 344 Kb, 档案已发布: May 14, 2004
Application Note 1085 FPD-Link PCB and Interconnect Design-In Guidelines
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Receiver Skew Margin for Channel Link I and FPD Link I Devices
PDF, 418 Kb, 档案已发布: Jan 13, 2016
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AN-1032 An Introduction to FPD-Link (Rev. C)
PDF, 185 Kb, 修订版: C, 档案已发布: Aug 8, 2017
The FPD-Linkchipsetarchitecturein conjunctionwith the LVDStechnologyprovidesthe highbandwidthinterfacenecessaryfor leadingedgedisplaytechnology.The conversionfromparallelTTL to serialLVDSallowsfor a narrowinterfacebetweengraphicscontrollerand panel.A narrowerinterfacemeanslowercablecost and simplifiesthe physicalconnectionthroug

系列: DS90CF386 (5)