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Documents DS90CR216A, DS90CR286A, DS90CR286A-Q1
SNLS043H – MAY 2000 – REVISED JANUARY 2016 DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver
28-Bit (or 21-Bit) Channel Link-66 MHz
1 Features 3 Description The DS90CR286A receiver converts the four LVDS
data streams back into parallel 28 bits of LVCMOS
data. Also available is the DS90CR216A receiver that
converts the three LVDS data streams back into
parallel 21 bits of LVCMOS data. The outputs of both
receivers strobe on the rising edge. 1 20 to 66 MHz Shift Clock Support
50% Duty Cycle on Receiver Output Clock
Best–in–Class Set and Hold Times on Rx Outputs
Rx Power Consumption < 270 mW (Typ) at 66
MHz Worst Case
Rx Power-Down Mode < 200 ОјW (Max)
ESD Rating > 7 kV (HBM), > 700 V (EIAJ)
PLL Requires No External Components
Compatible with TIA/EIA-644 LVDS Standard
Low Profile 56-Pin or 48-Pin DGG (TSSOP) …
