Datasheet Texas Instruments DS90CR216A — 数据表

制造商Texas Instruments
系列DS90CR216A
Datasheet Texas Instruments DS90CR216A

+ 3.3V上升沿数据选通LVDS接收器21位通道链接-66 MHz

数据表

DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz datasheet
PDF, 2.4 Mb, 修订版: H, 档案已发布: Jan 18, 2016
从文件中提取

价格

状态

DS90CR216AMTDDS90CR216AMTD/NOPBDS90CR216AMTDX/NOPB
Lifecycle StatusNRND (Not recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoYes

打包

DS90CR216AMTDDS90CR216AMTD/NOPBDS90CR216AMTDX/NOPB
N123
Pin484848
Package TypeDGGDGGDGG
Industry STD TermTSSOPTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY38381000
CarrierTUBETUBELARGE T&R
Device Marking>B>BDS90CR216AMTD
Width (mm)6.16.16.1
Length (mm)12.512.512.5
Thickness (mm)1.151.151.15
Pitch (mm).5.5.5
Max Height (mm)1.21.21.2
Mechanical Data下载下载下载

参数化

Parameters / ModelsDS90CR216AMTD
DS90CR216AMTD
DS90CR216AMTD/NOPB
DS90CR216AMTD/NOPB
DS90CR216AMTDX/NOPB
DS90CR216AMTDX/NOPB
Clock Max, MHz666666
Clock Min, MHz202020
Compression Ratio21 to 321 to 321 to 3
Data Throughput, Mbps138613861386
ESD, kV777
FunctionDeserializerDeserializerDeserializer
Input CompatibilityLVDSLVDSLVDS
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85
Output CompatibilityLVCMOSLVCMOSLVCMOS
Package GroupTSSOPTSSOPTSSOP
Package Size: mm2:W x L, PKG48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)
Parallel Bus Width, bits212121
ProtocolsChannel-Link IChannel-Link IChannel-Link I
RatingCatalogCatalogCatalog
Supply Voltage(s), V3.33.33.3

生态计划

DS90CR216AMTDDS90CR216AMTD/NOPBDS90CR216AMTDX/NOPB
RoHSSee ti.comCompliantCompliant

应用须知

  • CHANNEL LINK Moving and Shaping Information In Point-To-Point Applications
    PDF, 269 Kb, 档案已发布: Oct 5, 1998
  • Multi-Drop Channel-Link Operation
    PDF, 212 Kb, 档案已发布: Oct 4, 2004
  • AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines
    PDF, 245 Kb, 档案已发布: May 15, 2004
    Application Note 1108 Channel-Link PCB and Interconnect Design-In Guidelines
  • Receiver Skew Margin for Channel Link I and FPD Link I Devices
    PDF, 418 Kb, 档案已发布: Jan 13, 2016

模型线

制造商分类

  • Semiconductors> Interface> Serializer, Deserializer> Channel Link I