DS90CR285, DS90CR286
www.ti.com SNLS130C – MARCH 1999 – REVISED MARCH 2013 DS90CR285/DS90CR286 +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz
Check for Samples: DS90CR285, DS90CR286 FEATURES DESCRIPTION The DS90CR285 transmitter converts 28 bits of
LVCMOS/LVTTL data into four LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked
transmit clock is transmitted in parallel with the data
streams over a fifth LVDS link. Every cycle of the
transmit clock 28 bits of input data are sampled and
transmitted. The DS90CR286 receiver converts the
LVDS data streams back into 28 bits of
LVCMOS/LVTTL data. At a transmit clock frequency
of 66 MHz, 28 bits of TTL data are transmitted at a
rate of 462 Mbps per LVDS data channel. Using a 66
MHz clock, the data throughput is 1.848 Gbit/s (231
Mbytes/s). 1 2 Single +3.3V Supply
Chipset (Tx + Rx) Power Consumption B DS90CR285MTD/NOPB ACTIVE TSSOP DGG 56 34 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 85 DS90CR285MTD
>B DS90CR285MTDX NRND TSSOP DGG 56 1000 TBD Call TI Call TI -40 to 85 DS90CR285MTD
>B DS90CR285MTDX/NOPB ACTIVE TSSOP DGG 56 1000 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 85 DS90CR285MTD
>B DS90CR286MTD NRND TSSOP DGG 56 34 TBD Call TI Call TI DS90CR286MTD
>B DS90CR286MTD/NOPB NRND TSSOP DGG 56 34 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR DS90CR286MTD …
