Datasheet Texas Instruments DS90CR286AT-Q1 — 数据表
| 制造商 | Texas Instruments |
| 系列 | DS90CR286AT-Q1 |
3.3 V上升沿数据选通LVDS接收器28位Chan链接66 MHz
数据表
DS90CR286AT-Q1 3.3 V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link 66 MHz datasheet
PDF, 2.1 Mb, 修订版: A, 档案已发布: Dec 6, 2015
从文件中提取
价格
状态
| DS90CR286ATDGGQ1 | DS90CR286ATDGGRQ1 | |
|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes | No |
打包
| DS90CR286ATDGGQ1 | DS90CR286ATDGGRQ1 | |
|---|---|---|
| N | 1 | 2 |
| Pin | 56 | 56 |
| Package Type | DGG | DGG |
| Industry STD Term | TSSOP | TSSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G |
| Package QTY | 34 | 2000 |
| Carrier | TUBE | LARGE T&R |
| Device Marking | DS90CR286ATQ | DGG |
| Width (mm) | 6.1 | 6.1 |
| Length (mm) | 14 | 14 |
| Thickness (mm) | 1.15 | 1.15 |
| Pitch (mm) | .5 | .5 |
| Max Height (mm) | 1.2 | 1.2 |
| Mechanical Data | 下载 | 下载 |
参数化
| Parameters / Models | DS90CR286ATDGGQ1 | DS90CR286ATDGGRQ1 |
|---|---|---|
| Clock Max, MHz | 66 | 66 |
| Clock Min, MHz | 20 | 20 |
| Compression Ratio | 28 to 4 | 28 to 4 |
| Data Throughput, Mbps | 1848 | 1848 |
| ESD, kV | 4 | 4 |
| Function | Deserializer | Deserializer |
| Input Compatibility | LVDS | LVDS |
| Operating Temperature Range, C | -40 to 105 | -40 to 105 |
| Output Compatibility | LVCMOS | LVCMOS |
| Package Group | TSSOP | TSSOP |
| Package Size: mm2:W x L, PKG | 56TSSOP: 113 mm2: 8.1 x 14(TSSOP) | 56TSSOP: 113 mm2: 8.1 x 14(TSSOP) |
| Parallel Bus Width, bits | 28 | 28 |
| Protocols | Channel-Link I | Channel-Link I |
| Rating | Automotive | Automotive |
| Supply Voltage(s), V | 3.3 | 3.3 |
生态计划
| DS90CR286ATDGGQ1 | DS90CR286ATDGGRQ1 | |
|---|---|---|
| RoHS | Compliant | Compliant |
应用须知
- Receiver Skew Margin for Channel Link I and FPD Link I DevicesPDF, 418 Kb, 档案已发布: Jan 13, 2016
模型线
系列: DS90CR286AT-Q1 (2)
制造商分类
- Semiconductors> Interface> Serializer, Deserializer> Channel Link I