Datasheet Texas Instruments DS90UR241 — 数据表

制造商	Texas Instruments
系列	DS90UR241

数据表

价格

状态

打包

参数化

Parameters / Models	DS90UR241IVS/NOPB	DS90UR241IVSX/NOPB
Color Depth, bpp	18	18
Diagnostics	BIST	BIST
EMI Reduction	-	-
Function	Serializer	Serializer
Input Compatibility	LVCMOS	LVCMOS
Operating Temperature Range, C	-40 to 105	-40 to 105
Output Compatibility	FPD-Link LVDS	FPD-Link LVDS
Package Group	TQFP	TQFP
Package Size: mm2:W x L, PKG	48TQFP: 81 mm2: 9 x 9(TQFP)	48TQFP: 81 mm2: 9 x 9(TQFP)
Pixel Clock Min, MHz	5	5
Pixel Clock(Max), MHz	43	43
Rating	Catalog	Catalog
Signal Conditioning	Pre-Emphasis,VOD Select	Pre-Emphasis,VOD Select
Special Features	-	-
Total Throughput, Mbps	1032	1032

生态计划

应用须知

• 下载
  AN-2068 DS90UR241/124 Spread Spectrum Tolerance Support (Rev. B)
  PDF, 70 Kb, 修订版: B, 档案已发布: Apr 26, 2013
  Compliance to EMI limits is often a challenge. Spread spectrum clocking is commonly used to minimize EMI. The effect of modulating periodic signals, both clock and data, reduces the peak emissions by spreading the energy over a range of frequencies. The DS90UR241 and DS90UR124 chipset allows the use of spread spectrum clock and data inputs. The following is a discussion of spread spectrum clock ch
• 下载
  AN-1807 FPD-Link II Display SerDes Overview (Rev. B)
  PDF, 45 Kb, 修订版: B, 档案已发布: Apr 26, 2013
  TI’s FPD-Link II family of embedded clock LVDS SerDes provide enhanced features, and improved signal quality over prior generations of FPD-Link SerDes devices for Display applications. FPD-Link Chipsets serialized the wide parallel RGB buses down to 4 or 5 pairs of LVDS signaling depending upon the chipset. 18-bit RGB was serialized to three LVDS data lines and a LVDS clock, while 24-bit RGB was s
• 下载
  LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A)
  PDF, 101 Kb, 修订版: A, 档案已发布: Apr 29, 2013
  This application note introduces Texas Instrument’s LVDS devices with built-in pre-emphasis andequalization circuits, recommends when it makes sense to employ them with the FPD-Link II SER/DES,shows how to optimally interface them to the SER/DES, and discusses distance gains that may berealized with their signal enhancing functions.
• 下载
  Extending the Reach of a FPD-Link II Interface with Cable Drivers and Equalizers (Rev. A)
  PDF, 118 Kb, 修订版: A, 档案已发布: Apr 26, 2013
  TI's family of embedded clock LVDS SER/DES (FPD-link II) provides a 2-wire serial interface for displayapplications up to distances of 10 meters.
• 下载
  DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E)
  PDF, 170 Kb, 修订版: E, 档案已发布: Apr 29, 2013
  Reduction in system size, increase in system performance and savings in system cost are valuablebenefits that SER/DES devices (Serializers and Deserializers) bring to many system designers. Thesebenefits are the reason why SER/DES are integral pieces of many of today’s high-speed systems.One of the design constraints for these systems is the maximum transmission distance between a serializer

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制造商分类

• Semiconductors> Interface> Display & Imaging SerDes> FPD-Link II SerDes