Datasheet Texas Instruments DS90UR905QSQ/NOPB — 数据表

5-65MHz 24位彩色FPD-Link II串行器48-WQFN -40至105

数据表

PDF, 1.6 Mb, 修订版: H, 档案已发布: Jul 31, 2015

从文件中提取

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

Color Depth	24 bpp
Diagnostics	BIST,I2C Bus
EMI Reduction	SSC Compatible
Function	Serializer
Input Compatibility	LVCMOS
Operating Temperature Range	-40 to 105 C
Output Compatibility	FPD-Link II LVDS
Package Group	WQFN
Package Size: mm2:W x L	48WQFN: 49 mm2: 7 x 7(WQFN) PKG
Pixel Clock Min	5 MHz
Pixel Clock(Max)	65 MHz
Rating	Automotive
Signal Conditioning	De-Emphasis,VOD Select
Special Features	1.8V or 3.3V VDDIO,I2C Config
Total Throughput	1560 Mbps

RoHS

Compliant

下载
AN-1807 FPD-Link II Display SerDes Overview (Rev. B)
PDF, 45 Kb, 修订版: B, 档案已发布: Apr 26, 2013
TIвЂ™s FPD-Link II family of embedded clock LVDS SerDes provide enhanced features, and improved signal quality over prior generations of FPD-Link SerDes devices for Display applications. FPD-Link Chipsets serialized the wide parallel RGB buses down to 4 or 5 pairs of LVDS signaling depending upon the chipset. 18-bit RGB was serialized to three LVDS data lines and a LVDS clock, while 24-bit RGB was s
下载
LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A)
PDF, 101 Kb, 修订版: A, 档案已发布: Apr 29, 2013
This application note introduces Texas InstrumentвЂ™s LVDS devices with built-in pre-emphasis andequalization circuits, recommends when it makes sense to employ them with the FPD-Link II SER/DES,shows how to optimally interface them to the SER/DES, and discusses distance gains that may berealized with their signal enhancing functions.
下载
Extending the Reach of a FPD-Link II Interface with Cable Drivers and Equalizers (Rev. A)
PDF, 118 Kb, 修订版: A, 档案已发布: Apr 26, 2013
TI's family of embedded clock LVDS SER/DES (FPD-link II) provides a 2-wire serial interface for displayapplications up to distances of 10 meters.

系列: DS90UR905Q-Q1 (3)