Datasheet Texas Instruments DS92LV1021TMSAX/NOPB — 数据表

DS92LV1021, DS92LV1210
www.ti.com SNLS024C – MARCH 1999 – REVISED APRIL 2013 DS92LV1021 and DS92LV1210 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer
Check for Samples: DS92LV1021, DS92LV1210 FEATURES DESCRIPTION The DS92LV1021 transforms a 10-bit wide parallel
CMOS/TTL data bus into a single high speed Bus
LVDS serial data stream with embedded clock. The
DS92LV1210 receives the Bus LVDS serial data
stream and transforms it back into a 10-bit wide
parallel data bus and separates clock. The
DS92LV1021 may transmit data over heavily loaded
backplanes or 10 meters of cable. The reduced
cable, PCB trace count and connector size saves
cost and makes PCB design layout easier. Clock-todata and data-to-data skew are eliminated since one
output will transmit both clock and all data bits
serially. The powerdown pin is used to save power,
by reducing supply current when either device is not
in use. The Serializer has a synchronization mode
that should be activated upon power-up of the device.
The Deserializer will establish lock to this signal
within 1024 cycles, and will flag Lock status. The
embedded clock ensures a transition on the bus
every 12-bit cycle; eliminating transmission errors due
to charged cable conditions. The DS92LV1021 output
pins may be TRI-STATE to achieve a high …