Datasheet Texas Instruments DS92LV16 — 数据表
| 制造商 | Texas Instruments |
| 系列 | DS92LV16 |
16位总线LVDS串行器/解串器-25-80 MHz
数据表
DS92LV16 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz datasheet
PDF, 1.3 Mb, 修订版: H, 档案已发布: Apr 16, 2013
从文件中提取
价格
状态
| DS92LV16TVHG | DS92LV16TVHG/NOPB | DS92LV16TVHGX/NOPB | |
|---|---|---|---|
| Lifecycle Status | NRND (Not recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes | No | No |
打包
| DS92LV16TVHG | DS92LV16TVHG/NOPB | DS92LV16TVHGX/NOPB | |
|---|---|---|---|
| N | 1 | 2 | 3 |
| Pin | 80 | 80 | 80 |
| Package Type | PN | PN | PN |
| Industry STD Term | LQFP | LQFP | LQFP |
| JEDEC Code | S-PQFP-G | S-PQFP-G | S-PQFP-G |
| Package QTY | 119 | 119 | 1000 |
| Carrier | TUBE | TUBE | LARGE T&R |
| Device Marking | >B | DS92LV16TVHG | DS92LV16TVHG |
| Width (mm) | 12 | 12 | 12 |
| Length (mm) | 12 | 12 | 12 |
| Thickness (mm) | 1.4 | 1.4 | 1.4 |
| Pitch (mm) | .5 | .5 | .5 |
| Max Height (mm) | 1.6 | 1.6 | 1.6 |
| Mechanical Data | 下载 | 下载 | 下载 |
参数化
| Parameters / Models | DS92LV16TVHG | DS92LV16TVHG/NOPB | DS92LV16TVHGX/NOPB |
|---|---|---|---|
| ESD, kV | 2.5 | 2.5 | 2.5 |
| Function | SerDes | SerDes | SerDes |
| Input Compatibility | LVTTL,LVDS,BLVDS | LVTTL,LVDS,BLVDS | LVTTL,LVDS,BLVDS |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 | -40 to 85 |
| Output Compatibility | LVDS,BLVDS,LVTTL | LVDS,BLVDS,LVTTL | LVDS,BLVDS,LVTTL |
| Package Group | LQFP | LQFP | LQFP |
| Package Size: mm2:W x L, PKG | 80LQFP: 196 mm2: 14 x 14(LQFP) | 80LQFP: 196 mm2: 14 x 14(LQFP) | 80LQFP: 196 mm2: 14 x 14(LQFP) |
| Protocols | Channel-Link I | Channel-Link I | Channel-Link I |
| Rating | Catalog | Catalog | Catalog |
| Supply Voltage(s), V | 3.3 | 3.3 | 3.3 |
生态计划
| DS92LV16TVHG | DS92LV16TVHG/NOPB | DS92LV16TVHGX/NOPB | |
|---|---|---|---|
| RoHS | See ti.com | Compliant | Compliant |
应用须知
- How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask (Rev. A)PDF, 2.0 Mb, 修订版: A, 档案已发布: Apr 26, 2013
The following application report contains information that will help you validate signal quality on a BLVDS SER/DES link. How to capture an eye pattern, how to generate an eye mask, and how to validate signal quality are all explained in detail in this document. - DS92LV16 Power Up Reset (Rev. B)PDF, 26 Kb, 修订版: B, 档案已发布: Apr 26, 2013
DS92LV16 date code VS39AD and later (middle two date code numbers will be ≥ 39) have a minor metallayer change to the chip’s power up reset and pull up circuitry to ensure robust start up with very slowsupply ramp rates. This change is very minor. It does not affect device functionality, performance, orreliability and requires no re-qualification.All parts sampled or purchased directly fro - External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs (Rev. A)PDF, 8.3 Mb, 修订版: A, 档案已发布: Apr 26, 2013
This application report highlights how using external SerDes in conjunction with minimum current driveFPGA I/O can reduce FPGA’s internal noise and reap the benefits of a serial interface across the system.This may allow designers to use low end FPGAs with external SerDes to reduce cost and still have highanalog performance. - DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E)PDF, 170 Kb, 修订版: E, 档案已发布: Apr 29, 2013
Reduction in system size, increase in system performance and savings in system cost are valuablebenefits that SER/DES devices (Serializers and Deserializers) bring to many system designers. Thesebenefits are the reason why SER/DES are integral pieces of many of today’s high-speed systems.One of the design constraints for these systems is the maximum transmission distance between a serializer
模型线
系列: DS92LV16 (3)
制造商分类
- Semiconductors> Interface> Serializer, Deserializer> BLVDS/LVDS SerDes (<100 MHz)