Datasheet Texas Instruments DS92LV3222 — 数据表
| 制造商 | Texas Instruments |
| 系列 | DS92LV3222 |
20-50 MHz 32位通道Link II解串器
数据表
DS92LV3221/3222 20-50 MHz 32-Bit Channel Link II Serializer / Deserializer datasheet
PDF, 1.4 Mb, 修订版: C, 档案已发布: Apr 16, 2013
从文件中提取
价格
状态
| DS92LV3222TVS/NOPB | DS92LV3222TVSX/NOPB | |
|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | Yes |
打包
| DS92LV3222TVS/NOPB | DS92LV3222TVSX/NOPB | |
|---|---|---|
| N | 1 | 2 |
| Pin | 64 | 64 |
| Package Type | PAG | PAG |
| Industry STD Term | TQFP | TQFP |
| JEDEC Code | S-PQFP-G | S-PQFP-G |
| Package QTY | 160 | 1000 |
| Carrier | JEDEC TRAY (10+1) | LARGE T&R |
| Device Marking | TVS | TVS |
| Width (mm) | 10 | 10 |
| Length (mm) | 10 | 10 |
| Thickness (mm) | 1 | 1 |
| Pitch (mm) | .5 | .5 |
| Max Height (mm) | 1.2 | 1.2 |
| Mechanical Data | 下载 | 下载 |
参数化
| Parameters / Models | DS92LV3222TVS/NOPB | DS92LV3222TVSX/NOPB |
|---|---|---|
| Clock Max, MHz | 50 | 50 |
| Clock Min, MHz | 20 | 20 |
| Compression Ratio | 32 to 2 | 32 to 2 |
| ESD, kV | 4 | 4 |
| Function | Deserializer | Deserializer |
| Input Compatibility | LVDS | LVDS |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 |
| Output Compatibility | LVCMOS | LVCMOS |
| Package Group | TQFP | TQFP |
| Package Size: mm2:W x L, PKG | 64TQFP: 144 mm2: 12 x 12(TQFP) | 64TQFP: 144 mm2: 12 x 12(TQFP) |
| Parallel Bus Width, bits | 32 | 32 |
| Protocols | Channel-Link II | Channel-Link II |
| Rating | Catalog | Catalog |
生态计划
| DS92LV3222TVS/NOPB | DS92LV3222TVSX/NOPB | |
|---|---|---|
| RoHS | Compliant | Compliant |
应用须知
- Improving the Robustness of Channel Link Designs with Channel Link II Ser/Des (Rev. A)PDF, 62 Kb, 修订版: A, 档案已发布: Apr 26, 2013
This application note discusses how system designers are able to use Channel Link II ser/Des to improve old and new channel link designs. - DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E)PDF, 170 Kb, 修订版: E, 档案已发布: Apr 29, 2013
Reduction in system size, increase in system performance and savings in system cost are valuablebenefits that SER/DES devices (Serializers and Deserializers) bring to many system designers. Thesebenefits are the reason why SER/DES are integral pieces of many of today’s high-speed systems.One of the design constraints for these systems is the maximum transmission distance between a serializer
模型线
系列: DS92LV3222 (2)
制造商分类
- Semiconductors> Interface> Serializer, Deserializer> Channel Link II