Datasheet Texas Instruments DS92LV3242TVSX/NOPB — 数据表

20-85 MHz 32位通道Link II解串器64-TQFP -40至85

数据表

PDF, 1.9 Mb, 修订版: D, 档案已发布: Apr 16, 2013

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Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

Clock Max	85 MHz
Clock Min	20 MHz
Compression Ratio	32 to 4
ESD	4 kV
Function	Deserializer
Input Compatibility	LVDS
Operating Temperature Range	-40 to 85 C
Output Compatibility	LVCMOS
Package Group	TQFP
Package Size: mm2:W x L	64TQFP: 144 mm2: 12 x 12(TQFP) PKG
Parallel Bus Width	32 bits
Protocols	Channel-Link II
Rating	Catalog

RoHS

Compliant

Evaluation Modules & Boards: LV32EVK01
LV32EVK01 Evaluation Kit
Lifecycle Status: Active (Recommended for new designs)
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Improving the Robustness of Channel Link Designs with Channel Link II Ser/Des (Rev. A)
PDF, 62 Kb, 修订版: A, 档案已发布: Apr 26, 2013
This application note discusses how system designers are able to use Channel Link II ser/Des to improve old and new channel link designs.
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DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E)
PDF, 170 Kb, 修订版: E, 档案已发布: Apr 29, 2013
Reduction in system size, increase in system performance and savings in system cost are valuablebenefits that SER/DES devices (Serializers and Deserializers) bring to many system designers. Thesebenefits are the reason why SER/DES are integral pieces of many of todayвЂ™s high-speed systems.One of the design constraints for these systems is the maximum transmission distance between a serializer

系列: DS92LV3242 (2)