Datasheet Texas Instruments LM2502SQX/NOPB — 数据表

LM2502
www.ti.com SNLS176L – JANUARY 2004 – REVISED MAY 2013 Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer
Check for Samples: LM2502 FEATURES DESCRIPTION The LM2502 device is a dual link display interface
SERDES that adapts existing CPU / video busses to
a low power current-mode serial MPL link. The
chipset may also be used for a RGB565 application
with glue logic. The interconnect is reduced from 22
signals to only 3 active signals with the LM2502
chipset easing flex interconnect design, size and cost. 1 2 >300 Mbps Dual Link Raw Throughput
MPL Physical Layer (MPL-0)
Pin Selectable Master / Slave Mode
Frequency Reference Transport
Complete LVCMOS / MPL Translation
Interface Modes:
– 16-bit CPU, i80 or m68 Style
– RGB565 with Glue Logic
-30В°C to 85В°C Operating Range
Link Power Down Mode Reduces IDDZ < 10 ВµA
Dual Display Support (CS1* & CS2*)
Via-less MPL Interconnect Feature
3.0V Supply Voltage (VDD and VDDA)
Interfaces to 1.7V to 3.3V Logic (VDDIO) The Master Serializer (SER) resides beside an
application processor or baseband processor and …