LMK01801
www.ti.com SNAS573A – JANUARY 2012 – REVISED APRIL 2013 LMK01801 Dual Clock Divider Buffer
Check for Samples: LMK01801 1 Device Summary
1.1 Features 12 Pin Control Mode or MICROWIRE (SPI) Input and Output Frequency Range 1 kHz to 3.1
GHz Separate Input for Clock Output Banks A & B. 14 Differential Clock Outputs in Two Banks (A
& B)
– Output Bank A 8 Differential, Programmable Outputs (Up
to 8 as LVCMOS) Divider Values of 1 to 8, Even and Odd.
– Output Bank B 1.2 6 Differential Outputs (or up to 12 as
LVCMOS) Divides Values of 1 to 1045 or 1 to 8,
Even and Odd Analog and Digital Delays
50% Duty Cycle on All Outputs for All Divides
Separate Synchronization of Bank A and B.
RMS Additive Jitter 50 fs at 800 MHz
– 50 fs RMS Additive Jitter (12 kHz to 20 MHz)
Industrial Temperature Range: -40 to 85 В°C
3.15 V to 3.45 V Operation Target Applications High Performance Clock Distribution and Division
Wireless Infrastructure
Datacom and Telecom Clock Distribution
Medical Imaging
Test and Measurement
Military / Aerospace 1.3 Description
The LMK01801 is a very low noise solution for clocking systems that require distribution and frequency …
